[
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32b",
    "arguments": [
      "uint32_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32B"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cb",
    "arguments": [
      "uint32_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cd",
    "arguments": [
      "uint32_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Xm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32ch",
    "arguments": [
      "uint32_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cw",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32d",
    "arguments": [
      "uint32_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Xm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32X"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32h",
    "arguments": [
      "uint32_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32w",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ],
      [
        "MOVPRFX",
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaba[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ],
      [
        "MOVPRFX",
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALB"
      ],
      [
        "MOVPRFX",
        "SABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALB"
      ],
      [
        "MOVPRFX",
        "UABALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABALT"
      ],
      [
        "MOVPRFX",
        "SABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabalt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABALT"
      ],
      [
        "MOVPRFX",
        "UABALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ],
      [
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABD"
      ],
      [
        "MOVPRFX",
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ],
      [
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SABD"
      ],
      [
        "MOVPRFX",
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ],
      [
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UABD"
      ],
      [
        "MOVPRFX",
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlb[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svabdlt[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ],
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ],
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svabs[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacge[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacgt[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svacle[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaclt[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ],
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ],
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadalp[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLB"
      ],
      [
        "MOVPRFX",
        "ADCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLB"
      ],
      [
        "MOVPRFX",
        "ADCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLB"
      ],
      [
        "MOVPRFX",
        "ADCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLB"
      ],
      [
        "MOVPRFX",
        "ADCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLT"
      ],
      [
        "MOVPRFX",
        "ADCLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLT"
      ],
      [
        "MOVPRFX",
        "ADCLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLT"
      ],
      [
        "MOVPRFX",
        "ADCLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svadclt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADCLT"
      ],
      [
        "MOVPRFX",
        "ADCLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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      "pg": {
        "register": "Pg.H"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "MOVPRFX",
        "FADD"
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      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f32]_m",
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      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f32]_x",
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      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
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        "FADD"
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      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
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        "MOVPRFX",
        "FADD"
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      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f64]_x",
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      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
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    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    "instructions": [
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        "FADD"
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      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_f64]_z",
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      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FSUB"
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      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s16]_m",
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      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
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      "value": "svint16_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s16]_x",
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      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s16]_z",
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      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
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      "value": "svint16_t"
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      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    "instructions": [
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        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s32]_m",
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      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
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      "value": "svint32_t"
    },
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s32]_x",
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      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
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      "pg": {
        "register": "Pg.S"
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    "instructions": [
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        "ADD"
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      [
        "SUB"
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      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s32]_z",
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      "svint32_t op1",
      "int32_t op2"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
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        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
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    },
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    "instructions": [
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        "MOVPRFX",
        "ADD"
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      [
        "MOVPRFX",
        "ADD"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s64]_m",
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      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
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      "value": "svint64_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop2.D[*]"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "ADD"
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      [
        "MOVPRFX",
        "ADD"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s64]_x",
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      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
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    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
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      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    "instructions": [
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        "ADD"
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        "SUB"
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      [
        "ADD"
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      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s64]_z",
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      "svint64_t op1",
      "int64_t op2"
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      "value": "svint64_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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        "register": "Pg.D"
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    },
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    "instructions": [
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        "MOVPRFX",
        "ADD"
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      [
        "MOVPRFX",
        "ADD"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s8]_m",
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      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
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      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
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      "pg": {
        "register": "Pg.B"
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    },
    "Architectures": [
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    "instructions": [
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        "ADD"
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        "SUB"
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      [
        "ADD"
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      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_s8]_z",
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      "svint8_t op1",
      "int8_t op2"
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      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
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        "register": "Pg.B"
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    "instructions": [
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        "ADD"
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      [
        "MOVPRFX",
        "ADD"
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  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u16]_m",
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      "svuint16_t op1",
      "uint16_t op2"
    ],
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      "value": "svuint16_t"
    },
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        "register": "Zop1.H|Ztied1.H"
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        "register": "Zop2.H[*]"
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        "register": "Pg.H"
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    "Architectures": [
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    "instructions": [
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        "ADD"
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        "MOVPRFX",
        "ADD"
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  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u16]_x",
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      "svuint16_t op1",
      "uint16_t op2"
    ],
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      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H[*]|Ztied2.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    "instructions": [
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        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u16]_z",
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      "svuint16_t op1",
      "uint16_t op2"
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        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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      "pg": {
        "register": "Pg.H"
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    "Architectures": [
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    ],
    "instructions": [
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        "ADD"
      ],
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        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u32]_m",
    "arguments": [
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      "svuint32_t op1",
      "uint32_t op2"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    "instructions": [
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        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u32]_x",
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      "svuint32_t op1",
      "uint32_t op2"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    "instructions": [
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        "ADD"
      ],
      [
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      [
        "ADD"
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      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u32]_z",
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      "svuint32_t op1",
      "uint32_t op2"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
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        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "ADD"
      ],
      [
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        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u64]_m",
    "arguments": [
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      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ],
      [
        "ADD"
      ],
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ADD"
      ],
      [
        "MOVPRFX",
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadda[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t initial",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "initial": {
        "register": "Htied"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadda[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t initial",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "initial": {
        "register": "Stied"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadda[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t initial",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "initial": {
        "register": "Dtied"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddhnt[_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlb[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlbt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddlt[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ],
      [
        "MOVPRFX",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddp[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ],
      [
        "MOVPRFX",
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svaddv[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaddwt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrb[_u32base]_[s32]offset",
    "arguments": [
      "svuint32_t bases",
      "svint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrb[_u32base]_[u32]offset",
    "arguments": [
      "svuint32_t bases",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrb[_u64base]_[s64]offset",
    "arguments": [
      "svuint64_t bases",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrb[_u64base]_[u64]offset",
    "arguments": [
      "svuint64_t bases",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrd[_u32base]_[s32]index",
    "arguments": [
      "svuint32_t bases",
      "svint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrd[_u32base]_[u32]index",
    "arguments": [
      "svuint32_t bases",
      "svuint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrd[_u64base]_[s64]index",
    "arguments": [
      "svuint64_t bases",
      "svint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrd[_u64base]_[u64]index",
    "arguments": [
      "svuint64_t bases",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrh[_u32base]_[s32]index",
    "arguments": [
      "svuint32_t bases",
      "svint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrh[_u32base]_[u32]index",
    "arguments": [
      "svuint32_t bases",
      "svuint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrh[_u64base]_[s64]index",
    "arguments": [
      "svuint64_t bases",
      "svint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrh[_u64base]_[u64]index",
    "arguments": [
      "svuint64_t bases",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrw[_u32base]_[s32]index",
    "arguments": [
      "svuint32_t bases",
      "svint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrw[_u32base]_[u32]index",
    "arguments": [
      "svuint32_t bases",
      "svuint32_t indices"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "indices": {
        "register": "Zindices.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrw[_u64base]_[s64]index",
    "arguments": [
      "svuint64_t bases",
      "svint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svadrw[_u64base]_[u64]index",
    "arguments": [
      "svuint64_t bases",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "indices": {
        "register": "Zindices.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaesd[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AESD"
      ],
      [
        "AESD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaese[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AESE"
      ],
      [
        "AESE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaesimc[_u8]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AESIMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svaesmc[_u8]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AESMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "UXTH"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "UXTH"
      ],
      [
        "UXTW"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ],
      [
        "MOVPRFX",
        "UXTW"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "UXTH"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "UXTH"
      ],
      [
        "UXTW"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ],
      [
        "MOVPRFX",
        "UXTW"
      ],
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "AND"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svand[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "AND"
      ],
      [
        "MOVPRFX",
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svandv[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ANDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASRR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASR"
      ],
      [
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasr_wide[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ASRD"
      ],
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svasrd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ASRD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbcax[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ],
      [
        "MOVPRFX",
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbdep[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BDEP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbext[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbgrp[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BGRP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ],
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ],
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbic[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrka[_b]_m",
    "arguments": [
      "svbool_t inactive",
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ptied.B"
      },
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrka[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrkb[_b]_m",
    "arguments": [
      "svbool_t inactive",
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ptied.B"
      },
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrkb[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrkn[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Ptied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrkpa[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKPA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svbrkpb[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BRKPB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl1n[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL1N"
      ],
      [
        "MOVPRFX",
        "BSL1N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl2n[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL2N"
      ],
      [
        "MOVPRFX",
        "BSL2N"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svbsl[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ],
      [
        "MOVPRFX",
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ],
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcadd[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcadd[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CADD"
      ],
      [
        "MOVPRFX",
        "CADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcdot[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svint8_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CDOT"
      ],
      [
        "MOVPRFX",
        "CDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcdot[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CDOT"
      ],
      [
        "MOVPRFX",
        "CDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcdot_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svint8_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CDOT"
      ],
      [
        "MOVPRFX",
        "CDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcdot_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CDOT"
      ],
      [
        "MOVPRFX",
        "CDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_f16]",
    "arguments": [
      "svfloat16_t op",
      "svfloat16_t min",
      "svfloat16_t max"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.H"
      },
      "min": {
        "register": "Zreg2.H"
      },
      "op": {
        "register": "Zreg1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_f32]",
    "arguments": [
      "svfloat32_t op",
      "svfloat32_t min",
      "svfloat32_t max"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.S"
      },
      "min": {
        "register": "Zreg2.S"
      },
      "op": {
        "register": "Zreg1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_f64]",
    "arguments": [
      "svfloat64_t op",
      "svfloat64_t min",
      "svfloat64_t max"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.D"
      },
      "min": {
        "register": "Zreg2.D"
      },
      "op": {
        "register": "Zreg1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_s16]",
    "arguments": [
      "svint16_t op",
      "svint16_t min",
      "svint16_t max"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.H"
      },
      "min": {
        "register": "Zreg2.H"
      },
      "op": {
        "register": "Zreg1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_s32]",
    "arguments": [
      "svint32_t op",
      "svint32_t min",
      "svint32_t max"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.S"
      },
      "min": {
        "register": "Zreg2.S"
      },
      "op": {
        "register": "Zreg1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_s64]",
    "arguments": [
      "svint64_t op",
      "svint64_t min",
      "svint64_t max"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.D"
      },
      "min": {
        "register": "Zreg2.D"
      },
      "op": {
        "register": "Zreg1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_s8]",
    "arguments": [
      "svint8_t op",
      "svint8_t min",
      "svint8_t max"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.B"
      },
      "min": {
        "register": "Zreg2.B"
      },
      "op": {
        "register": "Zreg1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_u16]",
    "arguments": [
      "svuint16_t op",
      "svuint16_t min",
      "svuint16_t max"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.H"
      },
      "min": {
        "register": "Zreg2.H"
      },
      "op": {
        "register": "Zreg1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_u32]",
    "arguments": [
      "svuint32_t op",
      "svuint32_t min",
      "svuint32_t max"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.S"
      },
      "min": {
        "register": "Zreg2.S"
      },
      "op": {
        "register": "Zreg1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_u64]",
    "arguments": [
      "svuint64_t op",
      "svuint64_t min",
      "svuint64_t max"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.D"
      },
      "min": {
        "register": "Zreg2.D"
      },
      "op": {
        "register": "Zreg1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svclamp[_u8]",
    "arguments": [
      "svuint8_t op",
      "svuint8_t min",
      "svuint8_t max"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "max": {
        "register": "Zreg3.B"
      },
      "min": {
        "register": "Zreg2.B"
      },
      "op": {
        "register": "Zreg1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCLAMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t fallback",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t fallback",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t fallback",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t fallback",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t fallback",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t fallback",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t fallback",
      "svint16_t data"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t fallback",
      "svint32_t data"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t fallback",
      "svint64_t data"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t fallback",
      "svint8_t data"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Btied|Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t fallback",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t fallback",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t fallback",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t fallback",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Btied|Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t fallback",
      "svint16_t data"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t fallback",
      "svint32_t data"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t fallback",
      "svint64_t data"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t fallback",
      "svint8_t data"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Zfallback.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t fallback",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t fallback",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t fallback",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclasta[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t fallback",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Zfallback.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTA"
      ],
      [
        "MOVPRFX",
        "CLASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t fallback",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t fallback",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t fallback",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t fallback",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t fallback",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t fallback",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t fallback",
      "svint16_t data"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t fallback",
      "svint32_t data"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t fallback",
      "svint64_t data"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t fallback",
      "svint8_t data"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Btied|Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t fallback",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Htied|Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t fallback",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Stied|Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t fallback",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Dtied|Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t fallback",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Btied|Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t fallback",
      "svint16_t data"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t fallback",
      "svint32_t data"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t fallback",
      "svint64_t data"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t fallback",
      "svint8_t data"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Zfallback.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t fallback",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "fallback": {
        "register": "Zfallback.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t fallback",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "fallback": {
        "register": "Zfallback.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t fallback",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "fallback": {
        "register": "Zfallback.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclastb[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t fallback",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "fallback": {
        "register": "Zfallback.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLASTB"
      ],
      [
        "MOVPRFX",
        "CLASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ],
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcls[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ],
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svclz[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla_lane[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmla_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ],
      [
        "MOVPRFX",
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla_lane[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcmla_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLA"
      ],
      [
        "MOVPRFX",
        "CMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ],
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ],
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ],
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ],
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpeq_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpge_wide[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpgt_wide[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ],
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ],
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ],
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmple_wide[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
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      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svbool_t"
    },
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      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ],
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPGT"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_s8]",
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      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
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      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
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      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPHI"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ],
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ],
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmplt_wide[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ],
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ],
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMNE"
      ],
      [
        "FCMNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_n_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_n_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_n_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_n_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ],
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpne_wide[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMPNE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_n_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_n_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcmpuo[_n_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMUO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNOT"
      ],
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnot[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ],
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnt[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntb",
    "arguments": [],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntb_pat",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntd",
    "arguments": [],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntd_pat",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnth",
    "arguments": [],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcnth_pat",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntp_b16",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntp_b32",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntp_b64",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntp_b8",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntw",
    "arguments": [],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcntw_pat",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CNTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcompact[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "COMPACT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_f16]",
    "arguments": [
      "svfloat16_t x0",
      "svfloat16_t x1"
    ],
    "return_type": {
      "value": "svfloat16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_f32]",
    "arguments": [
      "svfloat32_t x0",
      "svfloat32_t x1"
    ],
    "return_type": {
      "value": "svfloat32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_f64]",
    "arguments": [
      "svfloat64_t x0",
      "svfloat64_t x1"
    ],
    "return_type": {
      "value": "svfloat64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_s16]",
    "arguments": [
      "svint16_t x0",
      "svint16_t x1"
    ],
    "return_type": {
      "value": "svint16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_s32]",
    "arguments": [
      "svint32_t x0",
      "svint32_t x1"
    ],
    "return_type": {
      "value": "svint32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_s64]",
    "arguments": [
      "svint64_t x0",
      "svint64_t x1"
    ],
    "return_type": {
      "value": "svint64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_s8]",
    "arguments": [
      "svint8_t x0",
      "svint8_t x1"
    ],
    "return_type": {
      "value": "svint8x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_u16]",
    "arguments": [
      "svuint16_t x0",
      "svuint16_t x1"
    ],
    "return_type": {
      "value": "svuint16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_u32]",
    "arguments": [
      "svuint32_t x0",
      "svuint32_t x1"
    ],
    "return_type": {
      "value": "svuint32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_u64]",
    "arguments": [
      "svuint64_t x0",
      "svuint64_t x1"
    ],
    "return_type": {
      "value": "svuint64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate2[_u8]",
    "arguments": [
      "svuint8_t x0",
      "svuint8_t x1"
    ],
    "return_type": {
      "value": "svuint8x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_f16]",
    "arguments": [
      "svfloat16_t x0",
      "svfloat16_t x1",
      "svfloat16_t x2"
    ],
    "return_type": {
      "value": "svfloat16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_f32]",
    "arguments": [
      "svfloat32_t x0",
      "svfloat32_t x1",
      "svfloat32_t x2"
    ],
    "return_type": {
      "value": "svfloat32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_f64]",
    "arguments": [
      "svfloat64_t x0",
      "svfloat64_t x1",
      "svfloat64_t x2"
    ],
    "return_type": {
      "value": "svfloat64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_s16]",
    "arguments": [
      "svint16_t x0",
      "svint16_t x1",
      "svint16_t x2"
    ],
    "return_type": {
      "value": "svint16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_s32]",
    "arguments": [
      "svint32_t x0",
      "svint32_t x1",
      "svint32_t x2"
    ],
    "return_type": {
      "value": "svint32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_s64]",
    "arguments": [
      "svint64_t x0",
      "svint64_t x1",
      "svint64_t x2"
    ],
    "return_type": {
      "value": "svint64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_s8]",
    "arguments": [
      "svint8_t x0",
      "svint8_t x1",
      "svint8_t x2"
    ],
    "return_type": {
      "value": "svint8x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_u16]",
    "arguments": [
      "svuint16_t x0",
      "svuint16_t x1",
      "svuint16_t x2"
    ],
    "return_type": {
      "value": "svuint16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_u32]",
    "arguments": [
      "svuint32_t x0",
      "svuint32_t x1",
      "svuint32_t x2"
    ],
    "return_type": {
      "value": "svuint32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_u64]",
    "arguments": [
      "svuint64_t x0",
      "svuint64_t x1",
      "svuint64_t x2"
    ],
    "return_type": {
      "value": "svuint64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate3[_u8]",
    "arguments": [
      "svuint8_t x0",
      "svuint8_t x1",
      "svuint8_t x2"
    ],
    "return_type": {
      "value": "svuint8x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_f16]",
    "arguments": [
      "svfloat16_t x0",
      "svfloat16_t x1",
      "svfloat16_t x2",
      "svfloat16_t x3"
    ],
    "return_type": {
      "value": "svfloat16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_f32]",
    "arguments": [
      "svfloat32_t x0",
      "svfloat32_t x1",
      "svfloat32_t x2",
      "svfloat32_t x3"
    ],
    "return_type": {
      "value": "svfloat32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_f64]",
    "arguments": [
      "svfloat64_t x0",
      "svfloat64_t x1",
      "svfloat64_t x2",
      "svfloat64_t x3"
    ],
    "return_type": {
      "value": "svfloat64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_s16]",
    "arguments": [
      "svint16_t x0",
      "svint16_t x1",
      "svint16_t x2",
      "svint16_t x3"
    ],
    "return_type": {
      "value": "svint16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_s32]",
    "arguments": [
      "svint32_t x0",
      "svint32_t x1",
      "svint32_t x2",
      "svint32_t x3"
    ],
    "return_type": {
      "value": "svint32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_s64]",
    "arguments": [
      "svint64_t x0",
      "svint64_t x1",
      "svint64_t x2",
      "svint64_t x3"
    ],
    "return_type": {
      "value": "svint64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_s8]",
    "arguments": [
      "svint8_t x0",
      "svint8_t x1",
      "svint8_t x2",
      "svint8_t x3"
    ],
    "return_type": {
      "value": "svint8x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_u16]",
    "arguments": [
      "svuint16_t x0",
      "svuint16_t x1",
      "svuint16_t x2",
      "svuint16_t x3"
    ],
    "return_type": {
      "value": "svuint16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_u32]",
    "arguments": [
      "svuint32_t x0",
      "svuint32_t x1",
      "svuint32_t x2",
      "svuint32_t x3"
    ],
    "return_type": {
      "value": "svuint32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_u64]",
    "arguments": [
      "svuint64_t x0",
      "svuint64_t x1",
      "svuint64_t x2",
      "svuint64_t x3"
    ],
    "return_type": {
      "value": "svuint64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcreate4[_u8]",
    "arguments": [
      "svuint8_t x0",
      "svuint8_t x1",
      "svuint8_t x2",
      "svuint8_t x3"
    ],
    "return_type": {
      "value": "svuint8x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f32]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f64]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f16[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVT"
      ]
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    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svint16_t op"
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      "value": "svfloat16_t"
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        "SCVTF"
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  {
    "SIMD_ISA": "SVE",
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      "svint16_t op"
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        "register": "Zop.H|Ztied.H"
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        "SCVTF"
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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      "svint32_t op"
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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  {
    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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        "register": "Pg.H"
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      "svuint32_t op"
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      "value": "svfloat16_t"
    },
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        "register": "Zinactive.H|Ztied.H"
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      "op": {
        "register": "Zop.S"
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  {
    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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        "MOVPRFX",
        "UCVTF"
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    "SIMD_ISA": "SVE",
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  {
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
    "name": "svcvt_f32[_f16]_m",
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        "FCVT"
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  {
    "SIMD_ISA": "SVE",
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  {
    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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      "svfloat64_t op"
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        "register": "Zinactive.S|Ztied.S"
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  {
    "SIMD_ISA": "SVE",
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    "arguments": [
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      "svfloat64_t op"
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    },
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  {
    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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  {
    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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    "instructions": [
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      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f32[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f32[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f16]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f32]_m",
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      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVT"
      ],
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s32]_m",
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      "svfloat64_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
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      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ],
      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ],
      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ],
      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u32]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ],
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_f64[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s16[_f16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s16[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s16[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f16]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f32]_x",
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      "svfloat32_t op"
    ],
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    },
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        "register": "Zop.S|Ztied.S"
      },
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    ],
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        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f64]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
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        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
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      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f64]_x",
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      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s32[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f16]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f32]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ],
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_s64[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u16[_f16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u16[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u16[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f16]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f64]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u32[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f16]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f32]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ],
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svcvt_u64[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtlt_f32[_f16]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtlt_f32[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.H"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtlt_f64[_f32]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.D"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtlt_f64[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.S"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtnt_f16[_f32]_m",
    "arguments": [
      "svfloat16_t even",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtnt_f16[_f32]_x",
    "arguments": [
      "svfloat16_t even",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTNT"
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    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtnt_f32[_f64]_m",
    "arguments": [
      "svfloat32_t even",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.D"
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      "pg": {
        "register": "Pg.D"
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      "A64"
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    "instructions": [
      [
        "FCVTNT"
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtnt_f32[_f64]_x",
    "arguments": [
      "svfloat32_t even",
      "svbool_t pg",
      "svfloat64_t op"
    ],
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      "value": "svfloat32_t"
    },
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      "even": {
        "register": "Ztied.S"
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      "op": {
        "register": "Zop.D"
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        "register": "Pg.D"
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      "A64"
    ],
    "instructions": [
      [
        "FCVTNT"
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtx_f32[_f64]_m",
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      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
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      "A64"
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      [
        "FCVTX"
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      [
        "MOVPRFX",
        "FCVTX"
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtx_f32[_f64]_x",
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      "svbool_t pg",
      "svfloat64_t op"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
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    "Architectures": [
      "A64"
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      [
        "FCVTX"
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      [
        "MOVPRFX",
        "FCVTX"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtx_f32[_f64]_z",
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      "svbool_t pg",
      "svfloat64_t op"
    ],
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      "value": "svfloat32_t"
    },
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      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
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      "A64"
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    "instructions": [
      [
        "MOVPRFX",
        "FCVTX"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtxnt_f32[_f64]_m",
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      "svfloat32_t even",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.D"
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      "pg": {
        "register": "Pg.D"
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      "A64"
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    "instructions": [
      [
        "FCVTXNT"
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svcvtxnt_f32[_f64]_x",
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      "svfloat32_t even",
      "svbool_t pg",
      "svfloat64_t op"
    ],
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      "value": "svfloat32_t"
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        "register": "Ztied.S"
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      "op": {
        "register": "Zop.D"
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        "register": "Pg.D"
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        "FCVTXNT"
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    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
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        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H"
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      "pg": {
        "register": "Pg.H"
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        "FDIV"
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      [
        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f16]_x",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
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      "pg": {
        "register": "Pg.H"
      }
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        "FDIV"
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      [
        "FDIVR"
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      [
        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f16]_z",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
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        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
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        "register": "Pg.H"
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        "MOVPRFX",
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      [
        "MOVPRFX",
        "FDIVR"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f32]_m",
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      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S"
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      "pg": {
        "register": "Pg.S"
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        "FDIV"
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      [
        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f32]_x",
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      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
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      "pg": {
        "register": "Pg.S"
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    "instructions": [
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        "FDIV"
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      [
        "FDIVR"
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      [
        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f32]_z",
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      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
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        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
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        "register": "Pg.S"
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        "MOVPRFX",
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      [
        "MOVPRFX",
        "FDIVR"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f64]_m",
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      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
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        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
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      "pg": {
        "register": "Pg.D"
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        "FDIV"
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        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_f64]_x",
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      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
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      "value": "svfloat64_t"
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        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop2.D|Ztied2.D"
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        "register": "Pg.D"
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        "FDIV"
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        "FDIVR"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat64_t op1",
      "svfloat64_t op2"
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      "value": "svfloat64_t"
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        "register": "Zop1.D"
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        "MOVPRFX",
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      [
        "MOVPRFX",
        "FDIVR"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_f16]_m",
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      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
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      "value": "svfloat16_t"
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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      "pg": {
        "register": "Pg.H"
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    "Architectures": [
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    "instructions": [
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        "FDIV"
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        "MOVPRFX",
        "FDIV"
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  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
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      "value": "svfloat16_t"
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        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H[*]|Ztied2.H[*]"
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      "pg": {
        "register": "Pg.H"
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_f16]_z",
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      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
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        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
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      "value": "svfloat32_t"
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    "Arguments_Preparation": {
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        "register": "Zop1.S|Ztied1.S"
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        "register": "Zop2.S[*]"
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        "FDIV"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
      "float32_t op2"
    ],
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    "Arguments_Preparation": {
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    "instructions": [
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  {
    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
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    ],
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  {
    "SIMD_ISA": "SVE",
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      "svfloat64_t op1",
      "float64_t op2"
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        "register": "Zop1.D|Ztied1.D"
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        "register": "Zop2.D[*]"
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  {
    "SIMD_ISA": "SVE",
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  {
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    "SIMD_ISA": "SVE",
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      "svint32_t op1",
      "int32_t op2"
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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      "svint64_t op1",
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    ],
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  {
    "SIMD_ISA": "SVE",
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      "svint64_t op1",
      "int64_t op2"
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    "Arguments_Preparation": {
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      "pg": {
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    "Architectures": [
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    "instructions": [
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      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIV"
      ],
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIV"
      ],
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIV"
      ],
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "UDIV"
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      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "UDIV"
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      [
        "UDIVR"
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      [
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        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdiv[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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      [
        "FDIV"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
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        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
        "FDIV"
      ],
      [
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        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FDIVR"
      ],
      [
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        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
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        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FDIVR"
      ],
      [
        "FDIV"
      ],
      [
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        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "FDIV"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "FDIV"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIVR"
      ],
      [
        "FDIV"
      ],
      [
        "MOVPRFX",
        "FDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FDIVR"
      ],
      [
        "MOVPRFX",
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDIVR"
      ],
      [
        "SDIV"
      ],
      [
        "MOVPRFX",
        "SDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SDIVR"
      ],
      [
        "MOVPRFX",
        "SDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDIVR"
      ],
      [
        "UDIV"
      ],
      [
        "MOVPRFX",
        "UDIVR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdivr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UDIVR"
      ],
      [
        "MOVPRFX",
        "UDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot[_f32_f16]",
    "arguments": [
      "svfloat32_t zda",
      "svfloat16_t zn",
      "svfloat16_t zm"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot[_s32_s16]",
    "arguments": [
      "svint32_t zda",
      "svint16_t zn",
      "svint16_t zm"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot[_u32_u16]",
    "arguments": [
      "svuint32_t zda",
      "svuint16_t zn",
      "svuint16_t zm"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot_lane[_f32_f16]",
    "arguments": [
      "svfloat32_t zda",
      "svfloat16_t zn",
      "svfloat16_t zm",
      "uint64_t imm_idx"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_idx": {
        "immediate": "imm1"
      },
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svint8_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot_lane[_s32_s16]",
    "arguments": [
      "svint32_t zda",
      "svint16_t zn",
      "svint16_t zm",
      "uint64_t imm_idx"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_idx": {
        "immediate": "imm1"
      },
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ],
      [
        "MOVPRFX",
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint8_t op2",
      "svuint8_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svdot_lane[_u32_u16]",
    "arguments": [
      "svuint32_t zda",
      "svuint16_t zn",
      "svuint16_t zm",
      "uint64_t imm_idx"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_idx": {
        "immediate": "imm1"
      },
      "zda": {
        "register": "Zreg1.S"
      },
      "zm": {
        "register": "Zreg3.H"
      },
      "zn": {
        "register": "Zreg2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdot_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ],
      [
        "MOVPRFX",
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_b16",
    "arguments": [
      "bool op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_b32",
    "arguments": [
      "bool op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_b64",
    "arguments": [
      "bool op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_b8",
    "arguments": [
      "bool op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f16",
    "arguments": [
      "float16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f16_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "float16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f16_x",
    "arguments": [
      "svbool_t pg",
      "float16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f16_z",
    "arguments": [
      "svbool_t pg",
      "float16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f32",
    "arguments": [
      "float32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f32_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "float32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f32_x",
    "arguments": [
      "svbool_t pg",
      "float32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f32_z",
    "arguments": [
      "svbool_t pg",
      "float32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f64",
    "arguments": [
      "float64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f64_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "float64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.D"
      },
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f64_x",
    "arguments": [
      "svbool_t pg",
      "float64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_f64_z",
    "arguments": [
      "svbool_t pg",
      "float64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s16",
    "arguments": [
      "int16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s16_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "int16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s16_x",
    "arguments": [
      "svbool_t pg",
      "int16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s16_z",
    "arguments": [
      "svbool_t pg",
      "int16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s32",
    "arguments": [
      "int32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s32_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "int32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s32_x",
    "arguments": [
      "svbool_t pg",
      "int32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s32_z",
    "arguments": [
      "svbool_t pg",
      "int32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s64",
    "arguments": [
      "int64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s64_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "int64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.D"
      },
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s64_x",
    "arguments": [
      "svbool_t pg",
      "int64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s64_z",
    "arguments": [
      "svbool_t pg",
      "int64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s8",
    "arguments": [
      "int8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s8_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "int8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.B"
      },
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s8_x",
    "arguments": [
      "svbool_t pg",
      "int8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_s8_z",
    "arguments": [
      "svbool_t pg",
      "int8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u16",
    "arguments": [
      "uint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u16_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "uint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u16_x",
    "arguments": [
      "svbool_t pg",
      "uint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u16_z",
    "arguments": [
      "svbool_t pg",
      "uint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Hop|Wop"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u32",
    "arguments": [
      "uint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u32_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "uint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u32_x",
    "arguments": [
      "svbool_t pg",
      "uint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u32_z",
    "arguments": [
      "svbool_t pg",
      "uint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Sop|Wop"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u64",
    "arguments": [
      "uint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u64_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "uint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.D"
      },
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u64_x",
    "arguments": [
      "svbool_t pg",
      "uint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u64_z",
    "arguments": [
      "svbool_t pg",
      "uint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Dop|Xop"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u8",
    "arguments": [
      "uint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u8_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "uint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Ztied.B"
      },
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "FCPY"
      ],
      [
        "CPY"
      ],
      [
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u8_x",
    "arguments": [
      "svbool_t pg",
      "uint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP"
      ],
      [
        "FCPY"
      ],
      [
        "FDUP"
      ],
      [
        "DUPM"
      ],
      [
        "DUP"
      ],
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup[_n]_u8_z",
    "arguments": [
      "svbool_t pg",
      "uint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Bop|Wop"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CPY"
      ],
      [
        "DUP",
        "FCPY"
      ],
      [
        "DUP",
        "CPY"
      ],
      [
        "MOVPRFX",
        "CPY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_f16]",
    "arguments": [
      "svfloat16_t data",
      "uint16_t index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "index": {
        "register": "Zindex.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_f32]",
    "arguments": [
      "svfloat32_t data",
      "uint32_t index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "index": {
        "register": "Zindex.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_f64]",
    "arguments": [
      "svfloat64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "index": {
        "register": "Zindex.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_s16]",
    "arguments": [
      "svint16_t data",
      "uint16_t index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "index": {
        "register": "Zindex.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_s32]",
    "arguments": [
      "svint32_t data",
      "uint32_t index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "index": {
        "register": "Zindex.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_s64]",
    "arguments": [
      "svint64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "index": {
        "register": "Zindex.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_s8]",
    "arguments": [
      "svint8_t data",
      "uint8_t index"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "index": {
        "register": "Zindex.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_u16]",
    "arguments": [
      "svuint16_t data",
      "uint16_t index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.H"
      },
      "index": {
        "register": "Zindex.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_u32]",
    "arguments": [
      "svuint32_t data",
      "uint32_t index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.S"
      },
      "index": {
        "register": "Zindex.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_u64]",
    "arguments": [
      "svuint64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D"
      },
      "index": {
        "register": "Zindex.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdup_lane[_u8]",
    "arguments": [
      "svuint8_t data",
      "uint8_t index"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.B"
      },
      "index": {
        "register": "Zindex.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_b16",
    "arguments": [
      "bool x0",
      "bool x1",
      "bool x2",
      "bool x3",
      "bool x4",
      "bool x5",
      "bool x6",
      "bool x7"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_b32",
    "arguments": [
      "bool x0",
      "bool x1",
      "bool x2",
      "bool x3"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_b64",
    "arguments": [
      "bool x0",
      "bool x1"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_b8",
    "arguments": [
      "bool x0",
      "bool x1",
      "bool x2",
      "bool x3",
      "bool x4",
      "bool x5",
      "bool x6",
      "bool x7",
      "bool x8",
      "bool x9",
      "bool x10",
      "bool x11",
      "bool x12",
      "bool x13",
      "bool x14",
      "bool x15"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_f16",
    "arguments": [
      "float16_t x0",
      "float16_t x1",
      "float16_t x2",
      "float16_t x3",
      "float16_t x4",
      "float16_t x5",
      "float16_t x6",
      "float16_t x7"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_f32",
    "arguments": [
      "float32_t x0",
      "float32_t x1",
      "float32_t x2",
      "float32_t x3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_f64",
    "arguments": [
      "float64_t x0",
      "float64_t x1"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_s16",
    "arguments": [
      "int16_t x0",
      "int16_t x1",
      "int16_t x2",
      "int16_t x3",
      "int16_t x4",
      "int16_t x5",
      "int16_t x6",
      "int16_t x7"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_s32",
    "arguments": [
      "int32_t x0",
      "int32_t x1",
      "int32_t x2",
      "int32_t x3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_s64",
    "arguments": [
      "int64_t x0",
      "int64_t x1"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_s8",
    "arguments": [
      "int8_t x0",
      "int8_t x1",
      "int8_t x2",
      "int8_t x3",
      "int8_t x4",
      "int8_t x5",
      "int8_t x6",
      "int8_t x7",
      "int8_t x8",
      "int8_t x9",
      "int8_t x10",
      "int8_t x11",
      "int8_t x12",
      "int8_t x13",
      "int8_t x14",
      "int8_t x15"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_u16",
    "arguments": [
      "uint16_t x0",
      "uint16_t x1",
      "uint16_t x2",
      "uint16_t x3",
      "uint16_t x4",
      "uint16_t x5",
      "uint16_t x6",
      "uint16_t x7"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_u32",
    "arguments": [
      "uint32_t x0",
      "uint32_t x1",
      "uint32_t x2",
      "uint32_t x3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_u64",
    "arguments": [
      "uint64_t x0",
      "uint64_t x1"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq[_n]_u8",
    "arguments": [
      "uint8_t x0",
      "uint8_t x1",
      "uint8_t x2",
      "uint8_t x3",
      "uint8_t x4",
      "uint8_t x5",
      "uint8_t x6",
      "uint8_t x7",
      "uint8_t x8",
      "uint8_t x9",
      "uint8_t x10",
      "uint8_t x11",
      "uint8_t x12",
      "uint8_t x13",
      "uint8_t x14",
      "uint8_t x15"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_f16]",
    "arguments": [
      "svfloat16_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_f32]",
    "arguments": [
      "svfloat32_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_f64]",
    "arguments": [
      "svfloat64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_s16]",
    "arguments": [
      "svint16_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_s32]",
    "arguments": [
      "svint32_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_s64]",
    "arguments": [
      "svint64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_s8]",
    "arguments": [
      "svint8_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_u16]",
    "arguments": [
      "svuint16_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_u32]",
    "arguments": [
      "svuint32_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_u64]",
    "arguments": [
      "svuint64_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svdupq_lane[_u8]",
    "arguments": [
      "svuint8_t data",
      "uint64_t index"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Zdata.D|Zdata.Q"
      },
      "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": {
        "register": "Zindices_d.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ],
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveor3[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "EOR3"
      ],
      [
        "MOVPRFX",
        "EOR3"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ],
      [
        "EOR"
      ],
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveor[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "EOR"
      ],
      [
        "MOVPRFX",
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_s16]",
    "arguments": [
      "svint16_t odd",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_s32]",
    "arguments": [
      "svint32_t odd",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_s64]",
    "arguments": [
      "svint64_t odd",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_s8]",
    "arguments": [
      "svint8_t odd",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_u16]",
    "arguments": [
      "svuint16_t odd",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_u32]",
    "arguments": [
      "svuint32_t odd",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_u64]",
    "arguments": [
      "svuint64_t odd",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_n_u8]",
    "arguments": [
      "svuint8_t odd",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_s16]",
    "arguments": [
      "svint16_t odd",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_s32]",
    "arguments": [
      "svint32_t odd",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_s64]",
    "arguments": [
      "svint64_t odd",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_s8]",
    "arguments": [
      "svint8_t odd",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_u16]",
    "arguments": [
      "svuint16_t odd",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_u32]",
    "arguments": [
      "svuint32_t odd",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_u64]",
    "arguments": [
      "svuint64_t odd",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveorbt[_u8]",
    "arguments": [
      "svuint8_t odd",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "odd": {
        "register": "Zodd.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORBT"
      ],
      [
        "MOVPRFX",
        "EORBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_s16]",
    "arguments": [
      "svint16_t even",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_s32]",
    "arguments": [
      "svint32_t even",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_s64]",
    "arguments": [
      "svint64_t even",
      "svint64_t op1",
      "int64_t op2"
    ],
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      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_s8]",
    "arguments": [
      "svint8_t even",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
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      "op2": {
        "register": "Zop2.B[*]"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_u16]",
    "arguments": [
      "svuint16_t even",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
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      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_u32]",
    "arguments": [
      "svuint32_t even",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_u64]",
    "arguments": [
      "svuint64_t even",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
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    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_n_u8]",
    "arguments": [
      "svuint8_t even",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_s16]",
    "arguments": [
      "svint16_t even",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_s32]",
    "arguments": [
      "svint32_t even",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
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      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_s64]",
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      "svint64_t even",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_s8]",
    "arguments": [
      "svint8_t even",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_u16]",
    "arguments": [
      "svuint16_t even",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.H|Ztied.H"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_u32]",
    "arguments": [
      "svuint32_t even",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.S|Ztied.S"
      },
      "op1": {
        "register": "Zop1.S"
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      "op2": {
        "register": "Zop2.S"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_u64]",
    "arguments": [
      "svuint64_t even",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.D|Ztied.D"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "sveortb[_u8]",
    "arguments": [
      "svuint8_t even",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Zeven.B|Ztied.B"
      },
      "op1": {
        "register": "Zop1.B"
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      "op2": {
        "register": "Zop2.B"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "EORTB"
      ],
      [
        "MOVPRFX",
        "EORTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
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    },
    "Architectures": [
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    "instructions": [
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        "EORV"
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  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
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      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
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    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "EORV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "EORV"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "EORV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "sveorv[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexpa[_f16]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FEXPA"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexpa[_f32]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FEXPA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexpa[_f64]",
    "arguments": [
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FEXPA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 127
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 127
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 255
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 127
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svext[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 255
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ],
      [
        "MOVPRFX",
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTB"
      ],
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTB"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextb[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTH"
      ],
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTH"
      ],
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTH"
      ],
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTH"
      ],
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTH"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTH"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTH"
      ],
      [
        "MOVPRFX",
        "UXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTH"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svexth[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTW"
      ],
      [
        "MOVPRFX",
        "SXTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SXTW"
      ],
      [
        "MOVPRFX",
        "SXTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SXTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTW"
      ],
      [
        "MOVPRFX",
        "UXTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UXTW"
      ],
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svextw[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UXTW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_f16]",
    "arguments": [
      "svfloat16x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_f32]",
    "arguments": [
      "svfloat32x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_f64]",
    "arguments": [
      "svfloat64x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_s16]",
    "arguments": [
      "svint16x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_s32]",
    "arguments": [
      "svint32x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_s64]",
    "arguments": [
      "svint64x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_s8]",
    "arguments": [
      "svint8x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_u16]",
    "arguments": [
      "svuint16x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_u32]",
    "arguments": [
      "svuint32x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_u64]",
    "arguments": [
      "svuint64x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget2[_u8]",
    "arguments": [
      "svuint8x2_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_f16]",
    "arguments": [
      "svfloat16x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_f32]",
    "arguments": [
      "svfloat32x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_f64]",
    "arguments": [
      "svfloat64x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_s16]",
    "arguments": [
      "svint16x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_s32]",
    "arguments": [
      "svint32x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_s64]",
    "arguments": [
      "svint64x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_s8]",
    "arguments": [
      "svint8x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_u16]",
    "arguments": [
      "svuint16x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_u32]",
    "arguments": [
      "svuint32x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_u64]",
    "arguments": [
      "svuint64x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget3[_u8]",
    "arguments": [
      "svuint8x3_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_f16]",
    "arguments": [
      "svfloat16x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_f32]",
    "arguments": [
      "svfloat32x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_f64]",
    "arguments": [
      "svfloat64x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_s16]",
    "arguments": [
      "svint16x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_s32]",
    "arguments": [
      "svint32x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_s64]",
    "arguments": [
      "svint64x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_s8]",
    "arguments": [
      "svint8x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_u16]",
    "arguments": [
      "svuint16x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_u32]",
    "arguments": [
      "svuint32x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_u64]",
    "arguments": [
      "svuint64x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svget4[_u8]",
    "arguments": [
      "svuint8x4_t tuple",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ],
      [
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHADD"
      ],
      [
        "MOVPRFX",
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ],
      [
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhadd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHADD"
      ],
      [
        "MOVPRFX",
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistcnt[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTCNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistcnt[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTCNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistcnt[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTCNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistcnt[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTCNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistseg[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTSEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhistseg[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "HISTSEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ],
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ],
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsub[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHSUBR"
      ],
      [
        "SHSUB"
      ],
      [
        "MOVPRFX",
        "SHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SHSUBR"
      ],
      [
        "MOVPRFX",
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UHSUBR"
      ],
      [
        "UHSUB"
      ],
      [
        "MOVPRFX",
        "UHSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svhsubr[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UHSUBR"
      ],
      [
        "MOVPRFX",
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_s16",
    "arguments": [
      "int16_t base",
      "int16_t step"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_s32",
    "arguments": [
      "int32_t base",
      "int32_t step"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_s64",
    "arguments": [
      "int64_t base",
      "int64_t step"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "step": {
        "register": "Xstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_s8",
    "arguments": [
      "int8_t base",
      "int8_t step"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_u16",
    "arguments": [
      "uint16_t base",
      "uint16_t step"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_u32",
    "arguments": [
      "uint32_t base",
      "uint32_t step"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_u64",
    "arguments": [
      "uint64_t base",
      "uint64_t step"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "step": {
        "register": "Xstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svindex_u8",
    "arguments": [
      "uint8_t base",
      "uint8_t step"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Wbase"
      },
      "step": {
        "register": "Wstep"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ],
      [
        "INDEX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_f16]",
    "arguments": [
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Hop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_f32]",
    "arguments": [
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Sop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_f64]",
    "arguments": [
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Dop2|Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Hop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Sop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Dop2|Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Bop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Hop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Sop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Dop2|Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svinsr[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Bop2|Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INSR"
      ],
      [
        "INSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlasta[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTA"
      ],
      [
        "LASTA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlastb[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LASTB"
      ],
      [
        "LASTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1W"
      ],
      [
        "LD1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base"
    ],
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        "LD1D"
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        "LD1H"
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        "LD1B"
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        "LD1D"
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        "LD1B"
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        "LD1B"
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        "LD1W"
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  {
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        "LD1W"
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      [
        "LD1W"
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        "LD1W"
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      [
        "LD1W"
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        "LD1W"
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      [
        "LD1W"
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        "LD1W"
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      [
        "LD1W"
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        "LD1W"
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        "LD1W"
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        "LD1W"
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        "LD1D"
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  {
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      [
        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1_gather_[u32]index[_f32]",
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      "value": "svfloat32_t"
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        "LD1W"
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  {
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        "LD1W"
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  {
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        "LD1W"
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  {
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        "LD1W"
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  {
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        "LD1W"
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  {
    "SIMD_ISA": "SVE",
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        "LD1W"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1_gather_[u64]offset[_f64]",
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        "LD1D"
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    "SIMD_ISA": "SVE",
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        "LD1D"
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1H"
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        "LD1H"
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        "LD1W"
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        "LD1W"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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        "LD1H"
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        "LD1H"
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        "LD1W"
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        "LD1D"
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      [
        "LD1D"
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  {
    "SIMD_ISA": "SVE",
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        "LD1B"
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        "LD1B"
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1_vnum[_u16]",
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        "LD1H"
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1_vnum[_u32]",
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      [
        "LD1W"
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  {
    "SIMD_ISA": "SVE",
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        "LD1D"
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        "LD1D"
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1_vnum[_u8]",
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      "int64_t vnum"
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        "LD1B"
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      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_f16]",
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      "const float16_t *base"
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        "register": "Pg.H"
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    "instructions": [
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        "LD1ROH"
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      [
        "LD1ROH"
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      [
        "LD1ROH"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_f32]",
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    "instructions": [
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        "LD1ROW"
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      [
        "LD1ROW"
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      [
        "LD1ROW"
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  {
    "SIMD_ISA": "SVE",
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    "instructions": [
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        "LD1ROD"
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      [
        "LD1ROD"
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        "LD1ROD"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_s16]",
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      "const int16_t *base"
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        "register": "Pg.H"
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    "instructions": [
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        "LD1ROH"
      ],
      [
        "LD1ROH"
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      [
        "LD1ROH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_s32]",
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      "const int32_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
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        "register": "Pg.S"
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    ],
    "instructions": [
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        "LD1ROW"
      ],
      [
        "LD1ROW"
      ],
      [
        "LD1ROW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_s64]",
    "arguments": [
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      "const int64_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
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    "instructions": [
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        "LD1ROD"
      ],
      [
        "LD1ROD"
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      [
        "LD1ROD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1ROB"
      ],
      [
        "LD1ROB"
      ],
      [
        "LD1ROB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1ROH"
      ],
      [
        "LD1ROH"
      ],
      [
        "LD1ROH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1ROW"
      ],
      [
        "LD1ROW"
      ],
      [
        "LD1ROW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1ROD"
      ],
      [
        "LD1ROD"
      ],
      [
        "LD1ROD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ro[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1ROB"
      ],
      [
        "LD1ROB"
      ],
      [
        "LD1ROB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQB"
      ],
      [
        "LD1RQB"
      ],
      [
        "LD1RQB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ],
      [
        "LD1RQH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ],
      [
        "LD1RQW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ],
      [
        "LD1RQD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1rq[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1RQB"
      ],
      [
        "LD1RQB"
      ],
      [
        "LD1RQB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u32base]_offset_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u32base]_offset_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u32base]_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u32base]_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u64base]_offset_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u64base]_offset_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u64base]_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather[_u64base]_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[s32]offset_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[s32]offset_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[s64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[s64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[u32]offset_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[u32]offset_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[u64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_gather_[u64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_s16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1SB"
      ],
      [
        "LD1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1sb_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
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        "LD1SH"
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  {
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        "LD1SH"
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        "LD1SH"
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  {
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        "LD1SH"
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        "LD1SH"
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      [
        "LD1SH"
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        "LD1SH"
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      [
        "LD1SH"
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  {
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        "LD1SH"
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      [
        "LD1SH"
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  {
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        "LD1SH"
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      [
        "LD1SH"
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  {
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        "LD1SH"
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      [
        "LD1SH"
      ]
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  {
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        "LD1SH"
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      [
        "LD1SH"
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  {
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        "LD1SH"
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      [
        "LD1SH"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "LD1SH"
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      [
        "LD1SH"
      ]
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    "instructions": [
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        "LD1SW"
      ],
      [
        "LD1SW"
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  {
    "SIMD_ISA": "SVE",
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        "LD1SW"
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      [
        "LD1SW"
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  {
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        "LD1SW"
      ],
      [
        "LD1SW"
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  {
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        "LD1SW"
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      [
        "LD1SW"
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  {
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        "LD1SW"
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  {
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        "LD1SW"
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  {
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        "LD1SW"
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  {
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  {
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  {
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  {
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  {
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        "LD1SW"
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        "LD1SW"
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        "LD1SW"
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        "LD1SW"
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  {
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        "LD1SW"
      ],
      [
        "LD1SW"
      ]
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  {
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      "int64_t vnum"
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        "LD1SW"
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      [
        "LD1SW"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svuint32_t bases",
      "int64_t offset"
    ],
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    "instructions": [
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        "LD1B"
      ],
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u32base]_offset_u32",
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      "svuint32_t bases",
      "int64_t offset"
    ],
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      },
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      "pg": {
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u32base]_s32",
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      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
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        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u32base]_u32",
    "arguments": [
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      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u64base]_offset_s64",
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      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
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      "value": "svint64_t"
    },
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      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u64base]_offset_u64",
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      "svuint64_t bases",
      "int64_t offset"
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      "value": "svuint64_t"
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        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
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      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u64base]_s64",
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      "svuint64_t bases"
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      "value": "svint64_t"
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        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather[_u64base]_u64",
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      "svuint64_t bases"
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      "value": "svuint64_t"
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        "register": "Zbases.D"
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      "pg": {
        "register": "Pg.D"
      }
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      "A64"
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    "instructions": [
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[s32]offset_s32",
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      "const uint8_t *base",
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      "value": "svint32_t"
    },
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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      "pg": {
        "register": "Pg.S"
      }
    },
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    "instructions": [
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[s32]offset_u32",
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      "value": "svuint32_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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      "pg": {
        "register": "Pg.S"
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    "instructions": [
      [
        "LD1B"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[s64]offset_s64",
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      "value": "svint64_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.D"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.D"
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        "register": "Pg.D"
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    ],
    "instructions": [
      [
        "LD1B"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[u32]offset_s32",
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      "value": "svint32_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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      "pg": {
        "register": "Pg.S"
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      "A64"
    ],
    "instructions": [
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[u32]offset_u32",
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      "value": "svuint32_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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        "register": "Pg.S"
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    ],
    "instructions": [
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[u64]offset_s64",
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      "value": "svint64_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.D"
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        "register": "Pg.D"
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    ],
    "instructions": [
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_gather_[u64]offset_u64",
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.D"
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      "pg": {
        "register": "Pg.D"
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    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_s16",
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      "const uint8_t *base"
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      "value": "svint16_t"
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
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    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_s32",
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      "const uint8_t *base"
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      "value": "svint32_t"
    },
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.S"
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_s64",
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      "value": "svint64_t"
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "const uint8_t *base"
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      "value": "svuint16_t"
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
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    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_u32",
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        "register": "Xbase"
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      "pg": {
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    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "const uint8_t *base"
    ],
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      "value": "svuint64_t"
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_vnum_s16",
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      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_vnum_s32",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
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    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_vnum_s64",
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      "const uint8_t *base",
      "int64_t vnum"
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    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
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    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_vnum_u16",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
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      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1ub_vnum_u64",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1B"
      ],
      [
        "LD1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_index_s32",
    "arguments": [
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      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_index_u32",
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      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_offset_s32",
    "arguments": [
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      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_offset_u32",
    "arguments": [
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      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u32base]_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u64base]_index_s64",
    "arguments": [
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      "svuint64_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u64base]_index_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u64base]_offset_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1H"
      ],
      [
        "LD1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld1uh_gather[_u64base]_offset_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
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      "pg": {
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      "indices": {
        "register": "Zindices.D"
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      "pg": {
        "register": "Pg.D"
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      "A64"
    ],
    "instructions": [
      [
        "LD1W"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svint64_t"
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        "register": "Xbase"
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        "register": "Zoffsets.D"
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      "A64"
    ],
    "instructions": [
      [
        "LD1W"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1uw_gather_[s64]offset_u64",
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        "register": "Xbase"
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      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD1W"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1uw_gather_[u64]index_s64",
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      "const uint32_t *base",
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        "register": "Xbase"
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      "indices": {
        "register": "Zindices.D"
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    "instructions": [
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svuint64_t"
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        "register": "Xbase"
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      "indices": {
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    "instructions": [
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1uw_gather_[u64]offset_s64",
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      "value": "svint64_t"
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        "register": "Xbase"
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        "register": "Zoffsets.D"
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    "instructions": [
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld1uw_s64",
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      "value": "svint64_t"
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      [
        "LD1W"
      ],
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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    "instructions": [
      [
        "LD1W"
      ],
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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      "vnum * svcntd()": {
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    "instructions": [
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        "LD1W"
      ],
      [
        "LD1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "LD1W"
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      [
        "LD1W"
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        "LD2H"
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      [
        "LD2H"
      ]
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        "LD2W"
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        "LD2W"
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        "LD2D"
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      [
        "LD2D"
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    "instructions": [
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        "LD2H"
      ],
      [
        "LD2H"
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    "instructions": [
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        "LD2W"
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      [
        "LD2W"
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  {
    "SIMD_ISA": "SVE",
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        "LD2D"
      ],
      [
        "LD2D"
      ]
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        "LD2B"
      ],
      [
        "LD2B"
      ]
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        "LD2H"
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      [
        "LD2H"
      ]
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  {
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        "LD2W"
      ],
      [
        "LD2W"
      ]
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  {
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        "LD2D"
      ],
      [
        "LD2D"
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  {
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        "LD2B"
      ],
      [
        "LD2B"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_f16]",
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      "int64_t vnum"
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    ],
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        "LD2H"
      ],
      [
        "LD2H"
      ]
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  {
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    ],
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        "LD2W"
      ],
      [
        "LD2W"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_f64]",
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      "const float64_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
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        "register": "Pg.D"
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      "vnum * svcntd()": {
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      }
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    ],
    "instructions": [
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        "LD2D"
      ],
      [
        "LD2D"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_s16]",
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    ],
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    },
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        "register": "Xbase"
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      "vnum * svcnth()": {
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      }
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    ],
    "instructions": [
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        "LD2H"
      ],
      [
        "LD2H"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
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      "const int32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
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      },
      "pg": {
        "register": "Pg.S"
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      "vnum * svcntw()": {
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      }
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    ],
    "instructions": [
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        "LD2W"
      ],
      [
        "LD2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_s64]",
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      "const int64_t *base",
      "int64_t vnum"
    ],
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    },
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      },
      "pg": {
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      },
      "vnum * svcntd()": {
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      }
    },
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    ],
    "instructions": [
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        "LD2D"
      ],
      [
        "LD2D"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_s8]",
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      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint8x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "LD2B"
      ],
      [
        "LD2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_u16]",
    "arguments": [
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      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "LD2H"
      ],
      [
        "LD2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_u32]",
    "arguments": [
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      "const uint32_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD2W"
      ],
      [
        "LD2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LD2D"
      ],
      [
        "LD2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld2_vnum[_u8]",
    "arguments": [
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      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint8x2_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2B"
      ],
      [
        "LD2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base"
    ],
    "return_type": {
      "value": "svfloat32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base"
    ],
    "return_type": {
      "value": "svfloat64x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_s16]",
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      "svbool_t pg",
      "const int16_t *base"
    ],
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      "value": "svint16x3_t"
    },
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base"
    ],
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      "value": "svint32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base"
    ],
    "return_type": {
      "value": "svint64x3_t"
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
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      "value": "svint8x3_t"
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3B"
      ],
      [
        "LD3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
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      "value": "svuint16x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
      }
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    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64x3_t"
    },
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
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      "value": "svuint8x3_t"
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD3B"
      ],
      [
        "LD3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat16x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat64x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint8x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3B"
      ],
      [
        "LD3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3H"
      ],
      [
        "LD3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3W"
      ],
      [
        "LD3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3D"
      ],
      [
        "LD3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld3_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint8x3_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3B"
      ],
      [
        "LD3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base"
    ],
    "return_type": {
      "value": "svfloat32x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base"
    ],
    "return_type": {
      "value": "svfloat64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svint16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base"
    ],
    "return_type": {
      "value": "svint32x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base"
    ],
    "return_type": {
      "value": "svint64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint8x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4B"
      ],
      [
        "LD4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
    "return_type": {
      "value": "svuint8x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4B"
      ],
      [
        "LD4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat32x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
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      "value": "svint8x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
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      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LD4B"
      ],
      [
        "LD4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
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      "value": "svuint16x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4H"
      ],
      [
        "LD4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
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      "value": "svuint32x4_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
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      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4W"
      ],
      [
        "LD4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4D"
      ],
      [
        "LD4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svld4_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
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      "value": "svuint8x4_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.B"
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      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4B"
      ],
      [
        "LD4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1H"
      ],
      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_f32]",
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      "svbool_t pg",
      "const float32_t *base"
    ],
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      "value": "svfloat32_t"
    },
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      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_f64]",
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      "const float64_t *base"
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      "value": "svfloat64_t"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
      }
    },
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    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_s16]",
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      "svbool_t pg",
      "const int16_t *base"
    ],
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      "value": "svint16_t"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
      }
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      "A64"
    ],
    "instructions": [
      [
        "LDFF1H"
      ],
      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_s32]",
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      "svbool_t pg",
      "const int32_t *base"
    ],
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      "value": "svint32_t"
    },
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.S"
      }
    },
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    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_s64]",
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      "const int64_t *base"
    ],
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      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
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    },
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    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_s8]",
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      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1B"
      ],
      [
        "LDFF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_u16]",
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      "const uint16_t *base"
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      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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    ],
    "instructions": [
      [
        "LDFF1H"
      ],
      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_u32]",
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      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1B"
      ],
      [
        "LDFF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_f32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_index_f32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_index_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_index_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_offset_f32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_offset_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_offset_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u32base]_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_f64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_index_f64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_index_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_index_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_offset_f64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_offset_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ],
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_gather[_u64base]_offset_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
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    "return_type": {
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      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u32base]_offset_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u32base]_offset_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u32base]_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u32base]_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u64base]_offset_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u64base]_offset_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u64base]_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather[_u64base]_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[s32]offset_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[s32]offset_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[s64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[s64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[u32]offset_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[u32]offset_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[u64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_gather_[u64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_s16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_u16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ],
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_s16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_u16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sb_vnum_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sh_gather[_u32base]_index_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SH"
      ],
      [
        "LDFF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1sh_gather[_u32base]_index_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDFF1SH"
      ],
      [
        "LDFF1SH"
      ]
    ]
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  {
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        "LDFF1SH"
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        "LDFF1SW"
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        "LDFF1SW"
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        "LDFF1SW"
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        "LDFF1SW"
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        "LDFF1SW"
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        "LDFF1B"
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        "LDFF1B"
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  {
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  {
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  {
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      "svuint32_t indices"
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    "return_type": {
      "value": "svuint32_t"
    },
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        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
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        "register": "Pg.S"
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      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "value": "svint32_t"
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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        "register": "Pg.S"
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    "instructions": [
      [
        "LDFF1H"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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        "register": "Xbase"
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      "offsets": {
        "register": "Zoffsets.S"
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    "instructions": [
      [
        "LDFF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "value": "svint64_t"
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        "register": "Xbase"
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      "indices": {
        "register": "Zindices.D"
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      [
        "LDFF1H"
      ]
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  {
    "SIMD_ISA": "SVE",
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      [
        "LDFF1H"
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  {
    "SIMD_ISA": "SVE",
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        "LDFF1H"
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  {
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        "LDFF1H"
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  {
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    "instructions": [
      [
        "LDFF1H"
      ],
      [
        "LDFF1H"
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  {
    "SIMD_ISA": "SVE",
    "name": "svldff1uh_s64",
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    "instructions": [
      [
        "LDFF1H"
      ],
      [
        "LDFF1H"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svuint32_t"
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    "instructions": [
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        "LDFF1H"
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      [
        "LDFF1H"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "LDFF1H"
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      [
        "LDFF1H"
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  {
    "SIMD_ISA": "SVE",
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      "pg": {
        "register": "Pg.S"
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    "instructions": [
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        "LDFF1H"
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  {
    "SIMD_ISA": "SVE",
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      "pg": {
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  {
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        "LDFF1H"
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        "LDFF1H"
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  {
    "SIMD_ISA": "SVE",
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      "index * 4": {
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        "LDFF1W"
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      [
        "LDFF1W"
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  {
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    "instructions": [
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        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
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    "SIMD_ISA": "SVE",
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        "LDFF1W"
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      [
        "LDFF1W"
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        "LDFF1W"
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      [
        "LDFF1W"
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  {
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    "name": "svldff1uw_gather[_u64base]_s64",
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        "LDFF1W"
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  {
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    "name": "svldff1uw_gather[_u64base]_u64",
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        "LDFF1W"
      ]
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  {
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      "indices": {
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      "pg": {
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    "instructions": [
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        "LDFF1W"
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  {
    "SIMD_ISA": "SVE",
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    "instructions": [
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        "LDFF1W"
      ]
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  {
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    "instructions": [
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        "LDFF1W"
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        "LDFF1W"
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  {
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    "instructions": [
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        "LDFF1W"
      ]
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  {
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        "LDFF1W"
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  {
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        "LDFF1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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    "instructions": [
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        "LDFF1W"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "const uint32_t *base"
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      "pg": {
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    ],
    "instructions": [
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        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svldff1uw_u64",
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      "const uint32_t *base"
    ],
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
      }
    },
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    ],
    "instructions": [
      [
        "LDFF1W"
      ],
      [
        "LDFF1W"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svldff1uw_vnum_s64",
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      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
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      }
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    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldff1uw_vnum_u64",
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      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
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      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LDFF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_f16]",
    "arguments": [
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      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 4": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ],
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 8": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ],
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 4": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ],
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 8": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ],
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntb()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 4": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ],
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 8": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1D"
      ],
      [
        "LDNF1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntb()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_s16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_u16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_s16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_u16",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sb_vnum_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SB"
      ],
      [
        "LDNF1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_s32",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_s64",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_u32",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_u64",
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      "const int16_t *base"
    ],
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      "value": "svuint64_t"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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    },
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_vnum_s32",
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      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
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      "value": "svint32_t"
    },
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      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 2": {
        "register": "Xptr"
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        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ],
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_vnum_s64",
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      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
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      "value": "svint64_t"
    },
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        "register": "Xbase"
      },
      "base + vnum * svcntd() * 2": {
        "register": "Xptr"
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        "register": "Pg.D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ],
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_vnum_u32",
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      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
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      "value": "svuint32_t"
    },
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        "register": "Xbase"
      },
      "base + vnum * svcntw() * 2": {
        "register": "Xptr"
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      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ],
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sh_vnum_u64",
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      "const int16_t *base",
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        "register": "Xbase"
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      "base + vnum * svcntd() * 2": {
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        "register": "Pg.D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1SH"
      ],
      [
        "LDNF1SH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sw_s64",
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      "value": "svint64_t"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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      "A64"
    ],
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      [
        "LDNF1SW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sw_u64",
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      "svbool_t pg",
      "const int32_t *base"
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      "value": "svuint64_t"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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      "A64"
    ],
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      [
        "LDNF1SW"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sw_vnum_s64",
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      "const int32_t *base",
      "int64_t vnum"
    ],
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      "value": "svint64_t"
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        "register": "Xbase"
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      "base + vnum * svcntd() * 4": {
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        "register": "Pg.D"
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    },
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      "A64"
    ],
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      [
        "LDNF1SW"
      ],
      [
        "LDNF1SW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1sw_vnum_u64",
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      "svbool_t pg",
      "const int32_t *base",
      "int64_t vnum"
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      "value": "svuint64_t"
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        "register": "Xbase"
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      "base + vnum * svcntd() * 4": {
        "register": "Xptr"
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      "pg": {
        "register": "Pg.D"
      }
    },
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      "A64"
    ],
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      [
        "LDNF1SW"
      ],
      [
        "LDNF1SW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_s16",
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      "const uint8_t *base"
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
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      "const uint8_t *base"
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.S"
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    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
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  {
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
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    ],
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      [
        "LDNF1B"
      ]
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  {
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        "register": "Xbase"
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      "pg": {
        "register": "Pg.H"
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_u32",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_u64",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base"
    ],
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      "value": "svuint64_t"
    },
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      "base": {
        "register": "Xbase"
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      "pg": {
        "register": "Pg.D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_s16",
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      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "base + vnum * svcnth()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_s32",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw()": {
        "register": "Xptr"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_s64",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
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      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_u16",
    "arguments": [
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcnth()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_u32",
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1ub_vnum_u64",
    "arguments": [
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      "const uint8_t *base",
      "int64_t vnum"
    ],
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      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd()": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1B"
      ],
      [
        "LDNF1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_s32",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_s64",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_u32",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_u64",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_vnum_s32",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_vnum_s64",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_vnum_u32",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntw() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uh_vnum_u64",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 2": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1H"
      ],
      [
        "LDNF1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uw_s64",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uw_u64",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uw_vnum_s64",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 4": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ],
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnf1uw_vnum_u64",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "base + vnum * svcntd() * 4": {
        "register": "Xptr"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNF1W"
      ],
      [
        "LDNF1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1H"
      ],
      [
        "LDNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1[_f32]",
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        "LDNT1H"
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      [
        "LDNT1B"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]index[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices * 8": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices * 8": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "svuint64_t indices"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices * 8": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]offset[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1_gather_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "const float16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1H"
      ],
      [
        "LDNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "const float32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1W"
      ],
      [
        "LDNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "const float64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ],
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "const int16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1H"
      ],
      [
        "LDNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "const int32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1W"
      ],
      [
        "LDNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "const int64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ],
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1B"
      ],
      [
        "LDNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "const uint16_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1H"
      ],
      [
        "LDNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "const uint32_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1W"
      ],
      [
        "LDNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "const uint64_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1D"
      ],
      [
        "LDNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svldnt1_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "const uint8_t *base",
      "int64_t vnum"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1B"
      ],
      [
        "LDNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u32base]_offset_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u32base]_offset_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u32base]_s32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u32base]_u32",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u64base]_offset_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u64base]_offset_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u64base]_s64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather[_u64base]_u64",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[s64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[s64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[u32]offset_s32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[u32]offset_u32",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint32_t offsets"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[u64]offset_s64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svldnt1sb_gather_[u64]offset_u64",
    "arguments": [
      "svbool_t pg",
      "const int8_t *base",
      "svuint64_t offsets"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDNT1SB"
      ]
    ]
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        "register": "Pg.D"
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        "FLOGB"
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    "SIMD_ISA": "SVE",
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      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSLR"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsl_wide[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSRR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSRR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSR"
      ],
      [
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svlsr_wide[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmad[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmatch[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmatch[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmatch[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmatch[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
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      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ],
      [
        "MOVPRFX",
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H[*]|Ztied2.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S[*]|Ztied2.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s32]_z",
    "arguments": [
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      "svint32_t op1",
      "int32_t op2"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
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        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ],
      [
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMAX"
      ],
      [
        "MOVPRFX",
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ],
      [
        "MOVPRFX",
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmax[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
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      "value": "svuint16_t"
    },
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        "register": "Zop1.H|Ztied1.H"
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        "register": "Pg.H"
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        "UMAX"
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      [
        "UMAX"
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        "MOVPRFX",
        "UMAX"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svuint16_t op1",
      "svuint16_t op2"
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      "value": "svuint16_t"
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        "register": "Zop1.H"
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        "register": "Pg.H"
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        "MOVPRFX",
        "UMAX"
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      [
        "MOVPRFX",
        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2"
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      "value": "svuint32_t"
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        "register": "Zop1.S|Ztied1.S"
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        "UMAX"
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        "MOVPRFX",
        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2"
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        "register": "Zop1.S|Ztied1.S"
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        "register": "Zop2.S|Ztied2.S"
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        "register": "Pg.S"
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        "UMAX"
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      [
        "UMAX"
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      [
        "MOVPRFX",
        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2"
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        "register": "Zop1.S"
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        "register": "Pg.S"
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        "MOVPRFX",
        "UMAX"
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      [
        "MOVPRFX",
        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op1",
      "svuint64_t op2"
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      "value": "svuint64_t"
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        "register": "Zop1.D|Ztied1.D"
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        "register": "Zop2.D"
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        "register": "Pg.D"
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        "UMAX"
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      [
        "MOVPRFX",
        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op1",
      "svuint64_t op2"
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        "register": "Zop1.D|Ztied1.D"
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        "UMAX"
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        "UMAX"
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      [
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        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op1",
      "svuint64_t op2"
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        "register": "Zop1.D"
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        "register": "Zop2.D"
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  {
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      "svuint8_t op1",
      "svuint8_t op2"
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      "value": "svuint8_t"
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        "register": "Zop1.B|Ztied1.B"
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        "register": "Zop2.B"
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      "pg": {
        "register": "Pg.B"
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        "UMAX"
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        "MOVPRFX",
        "UMAX"
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  {
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        "register": "Zop1.B|Ztied1.B"
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        "register": "Zop2.B|Ztied2.B"
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        "register": "Pg.B"
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        "UMAX"
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        "register": "Zop1.B"
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      "op2": {
        "register": "Zop2.B"
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      "pg": {
        "register": "Pg.B"
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        "UMAX"
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        "UMAX"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat16_t op1",
      "svfloat16_t op2"
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      "value": "svfloat16_t"
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        "register": "Zop1.H|Ztied1.H"
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        "register": "Zop2.H"
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      "pg": {
        "register": "Pg.H"
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        "FMAXNM"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat16_t op1",
      "svfloat16_t op2"
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      "value": "svfloat16_t"
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        "register": "Zop1.H|Ztied1.H"
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        "register": "Zop2.H|Ztied2.H"
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        "FMAXNM"
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        "FMAXNM"
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    "SIMD_ISA": "SVE",
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      "svfloat16_t op2"
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        "register": "Zop1.H"
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        "FMAXNM"
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    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
      "svfloat32_t op2"
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        "register": "Zop1.S|Ztied1.S"
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        "FMAXNM"
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        "FMAXNM"
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    "SIMD_ISA": "SVE",
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      "svfloat32_t op2"
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        "register": "Zop1.S|Ztied1.S"
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        "FMAXNM"
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        "FMAXNM"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat32_t op2"
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        "FMAXNM"
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    "SIMD_ISA": "SVE",
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      "svfloat64_t op1",
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        "register": "Zop1.D|Ztied1.D"
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        "register": "Zop1.D|Ztied1.D"
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    "SIMD_ISA": "SVE",
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      "float16_t op2"
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        "register": "Ztied1.H"
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        "register": "Zop1.H|Ztied1.H"
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        "FMAXNM"
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    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
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        "register": "Zop1.S|Ztied1.S"
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  {
    "SIMD_ISA": "SVE",
    "name": "svmaxnm[_n_f64]_x",
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      "svfloat64_t op1",
      "float64_t op2"
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      "value": "svfloat64_t"
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    "Arguments_Preparation": {
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        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop2.D[*]|Ztied2.D[*]"
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    "instructions": [
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        "FMAXNM"
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        "FMAXNM"
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        "FMAXNM"
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmaxnm[_n_f64]_z",
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      "svfloat64_t op1",
      "float64_t op2"
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      "value": "svfloat64_t"
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    "Arguments_Preparation": {
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        "register": "Zop1.D"
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      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
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        "FMAXNM"
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        "FMAXNM"
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    "instructions": [
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  {
    "SIMD_ISA": "SVE2",
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      "svuint8_t op1",
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      "value": "svuint8_t"
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        "register": "Zop1.B|Ztied1.B"
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        "register": "Pg.D"
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        "FMAXV"
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        "SMAXV"
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        "register": "Zop.B"
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      "pg": {
        "register": "Pg.B"
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        "FMIN"
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        "register": "Zop1.H|Ztied1.H"
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        "FMIN"
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        "FMIN"
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        "register": "Zop1.H|Ztied1.H"
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        "SMIN"
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        "SMIN"
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    "SIMD_ISA": "SVE",
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      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
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      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ],
      [
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_s8]_z",
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      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMIN"
      ],
      [
        "MOVPRFX",
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
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      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
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      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
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      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u8]_m",
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      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
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      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u8]_x",
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      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
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      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ],
      [
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmin[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMIN"
      ],
      [
        "MOVPRFX",
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f16]_m",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f32]_x",
    "arguments": [
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      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f32]_z",
    "arguments": [
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      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
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        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_f64]_z",
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      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
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        "register": "Zop1.D"
      },
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      }
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    ],
    "instructions": [
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        "MOVPRFX",
        "FMINNM"
      ],
      [
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        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f16]_m",
    "arguments": [
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      "svfloat16_t op1",
      "float16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
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        "register": "Pg.S"
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    },
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      "A64"
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      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svfloat32_t"
    },
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Pg.S"
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      "A64"
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      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f32]_z",
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      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
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      "value": "svfloat32_t"
    },
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      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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        "register": "Pg.S"
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    },
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      "A64"
    ],
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      [
        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnm[_n_f64]_m",
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      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
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      "value": "svfloat64_t"
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        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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        "register": "Pg.D"
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      "A64"
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      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
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      "value": "svfloat64_t"
    },
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      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop2.D[*]|Ztied2.D[*]"
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      [
        "FMINNM"
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      [
        "FMINNM"
      ],
      [
        "FMINNM"
      ],
      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
        "register": "Pg.D"
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      "A64"
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      [
        "MOVPRFX",
        "FMINNM"
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      [
        "MOVPRFX",
        "FMINNM"
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      [
        "MOVPRFX",
        "FMINNM"
      ]
    ]
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  {
    "SIMD_ISA": "SVE2",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
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      "pg": {
        "register": "Pg.H"
      }
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      "A64"
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    "instructions": [
      [
        "FMINNMP"
      ],
      [
        "MOVPRFX",
        "FMINNMP"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminnmp[_f16]_x",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
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        "register": "Pg.H"
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      "A64"
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      [
        "FMINNMP"
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      [
        "MOVPRFX",
        "FMINNMP"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminnmp[_f32]_m",
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      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
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        "register": "Pg.S"
      }
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      "A64"
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    "instructions": [
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        "FMINNMP"
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      [
        "MOVPRFX",
        "FMINNMP"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminnmp[_f32]_x",
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      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S"
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        "register": "Pg.S"
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        "FMINNMP"
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        "MOVPRFX",
        "FMINNMP"
      ]
    ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminnmp[_f64]_m",
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      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
    },
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      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    "instructions": [
      [
        "FMINNMP"
      ],
      [
        "MOVPRFX",
        "FMINNMP"
      ]
    ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminnmp[_f64]_x",
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      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
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    ],
    "instructions": [
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        "FMINNMP"
      ],
      [
        "MOVPRFX",
        "FMINNMP"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svminnmv[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
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      "value": "float16_t"
    },
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      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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    ],
    "instructions": [
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        "FMINNMV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnmv[_f32]",
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      "svbool_t pg",
      "svfloat32_t op"
    ],
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      "value": "float32_t"
    },
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      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
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    ],
    "instructions": [
      [
        "FMINNMV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminnmv[_f64]",
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      "svfloat64_t op"
    ],
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      "value": "float64_t"
    },
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      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
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    ],
    "instructions": [
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        "FMINNMV"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_f16]_m",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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    },
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
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      "pg": {
        "register": "Pg.H"
      }
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    "Architectures": [
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    ],
    "instructions": [
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        "FMINP"
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      [
        "MOVPRFX",
        "FMINP"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_f16]_x",
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      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
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    ],
    "instructions": [
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        "FMINP"
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      [
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        "FMINP"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_f32]_m",
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      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "FMINP"
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      [
        "MOVPRFX",
        "FMINP"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_f32]_x",
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      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
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      "value": "svfloat32_t"
    },
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Pg.S"
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    "instructions": [
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        "FMINP"
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        "FMINP"
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    "SIMD_ISA": "SVE2",
    "name": "svminp[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
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    ],
    "instructions": [
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        "FMINP"
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      [
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        "FMINP"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_f64]_x",
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      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop2.D"
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    ],
    "instructions": [
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        "FMINP"
      ],
      [
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        "FMINP"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s16]_m",
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      "svint16_t op1",
      "svint16_t op2"
    ],
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      "value": "svint16_t"
    },
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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    ],
    "instructions": [
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        "SMINP"
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      [
        "MOVPRFX",
        "SMINP"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s16]_x",
    "arguments": [
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      "svint16_t op1",
      "svint16_t op2"
    ],
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      "value": "svint16_t"
    },
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        "register": "Zop1.H|Ztied1.H"
      },
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      },
      "pg": {
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    },
    "Architectures": [
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    ],
    "instructions": [
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        "SMINP"
      ],
      [
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        "SMINP"
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  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s32]_m",
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      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "SMINP"
      ],
      [
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        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
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      "value": "svint32_t"
    },
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        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
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    "Architectures": [
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    ],
    "instructions": [
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        "SMINP"
      ],
      [
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        "SMINP"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
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      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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    ],
    "instructions": [
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        "SMINP"
      ],
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        "SMINP"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s64]_x",
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      "svint64_t op1",
      "svint64_t op2"
    ],
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    },
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      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
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    ],
    "instructions": [
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        "SMINP"
      ],
      [
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        "SMINP"
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s8]_m",
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      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "SMINP"
      ],
      [
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        "SMINP"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_s8]_x",
    "arguments": [
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      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "SMINP"
      ],
      [
        "MOVPRFX",
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svminp[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ],
      [
        "MOVPRFX",
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svminv[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
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      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
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      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
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      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "FMAD"
      ],
      [
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FMLA"
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      [
        "MOVPRFX",
        "FMAD"
      ],
      [
        "MOVPRFX",
        "FMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
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      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
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      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
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      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "MLA"
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      [
        "MAD"
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      [
        "MAD"
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      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s16]_z",
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      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
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      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
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      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    "instructions": [
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        "MLA"
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      [
        "MAD"
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      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s32]_z",
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      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
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      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
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      "pg": {
        "register": "Pg.S"
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    },
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    "instructions": [
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        "MOVPRFX",
        "MLA"
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      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s64]_m",
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      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    "instructions": [
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        "MLA"
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      [
        "MOVPRFX",
        "MLA"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s64]_x",
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      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
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      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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        "MLA"
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      [
        "MAD"
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      [
        "MAD"
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      [
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        "MLA"
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  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_s64]_z",
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      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
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      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
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      "pg": {
        "register": "Pg.D"
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        "MOVPRFX",
        "MAD"
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      [
        "MOVPRFX",
        "MAD"
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    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
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      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
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    },
    "Architectures": [
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    ],
    "instructions": [
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        "MLA"
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      [
        "MOVPRFX",
        "MLA"
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  {
    "SIMD_ISA": "SVE",
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      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
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      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
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    "Architectures": [
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    "instructions": [
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        "MLA"
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        "MAD"
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      [
        "MAD"
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      [
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        "MLA"
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    "SIMD_ISA": "SVE",
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      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
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      "pg": {
        "register": "Pg.B"
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    ],
    "instructions": [
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        "MLA"
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        "MAD"
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      [
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        "MAD"
      ]
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      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
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    },
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        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
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      "pg": {
        "register": "Pg.H"
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    "instructions": [
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        "MLA"
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  {
    "SIMD_ISA": "SVE",
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      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H|Ztied2.H"
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      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
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      "pg": {
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    },
    "Architectures": [
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    ],
    "instructions": [
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        "MLA"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
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      "pg": {
        "register": "Pg.H"
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    },
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    ],
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        "MLA"
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        "MAD"
      ]
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  {
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      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
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        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
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      ],
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        "MLA"
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  {
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      "svuint32_t op1",
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      "uint32_t op3"
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
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        "register": "Zop2.S|Ztied2.S"
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      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
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      "pg": {
        "register": "Pg.S"
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    },
    "Architectures": [
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    ],
    "instructions": [
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      [
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      [
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        "MLA"
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    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
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      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "MLA"
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      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MAD"
      ],
      [
        "MAD"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLA"
      ],
      [
        "MOVPRFX",
        "MAD"
      ],
      [
        "MOVPRFX",
        "MAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla_lane[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmla_lane[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ],
      [
        "MOVPRFX",
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmla_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ],
      [
        "MOVPRFX",
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALB"
      ],
      [
        "MOVPRFX",
        "FMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALB"
      ],
      [
        "MOVPRFX",
        "FMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALB"
      ],
      [
        "MOVPRFX",
        "FMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALB"
      ],
      [
        "MOVPRFX",
        "SMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalb_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALB"
      ],
      [
        "MOVPRFX",
        "UMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALT"
      ],
      [
        "MOVPRFX",
        "FMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALT"
      ],
      [
        "MOVPRFX",
        "FMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLALT"
      ],
      [
        "MOVPRFX",
        "FMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLALT"
      ],
      [
        "MOVPRFX",
        "SMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlalt_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLALT"
      ],
      [
        "MOVPRFX",
        "UMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ],
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
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    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls_lane[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmls_lane[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmls_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLB"
      ],
      [
        "MOVPRFX",
        "FMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLB"
      ],
      [
        "MOVPRFX",
        "FMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLB"
      ],
      [
        "MOVPRFX",
        "FMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLB"
      ],
      [
        "MOVPRFX",
        "SMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslb_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLB"
      ],
      [
        "MOVPRFX",
        "UMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLT"
      ],
      [
        "MOVPRFX",
        "FMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLT"
      ],
      [
        "MOVPRFX",
        "FMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLSLT"
      ],
      [
        "MOVPRFX",
        "FMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSLT"
      ],
      [
        "MOVPRFX",
        "SMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2",
      "svuint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmlslt_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2",
      "svuint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSLT"
      ],
      [
        "MOVPRFX",
        "UMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmmla[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMMLA"
      ],
      [
        "MOVPRFX",
        "FMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmmla[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMMLA"
      ],
      [
        "MOVPRFX",
        "FMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmmla[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMMLA"
      ],
      [
        "MOVPRFX",
        "SMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmmla[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMMLA"
      ],
      [
        "MOVPRFX",
        "UMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmov[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_s16]",
    "arguments": [
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_s32]",
    "arguments": [
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_s64]",
    "arguments": [
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_u16]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_u32]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlb[_u64]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_s16]",
    "arguments": [
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_s32]",
    "arguments": [
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_s64]",
    "arguments": [
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_u16]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_u32]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmovlt[_u64]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSB"
      ],
      [
        "FMSB"
      ],
      [
        "FMLS"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMSB"
      ],
      [
        "MOVPRFX",
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MSB"
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      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
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      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MSB"
      ],
      [
        "MSB"
      ],
      [
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      ],
      [
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        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "MSB"
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        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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      ],
      [
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        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s8]_x",
    "arguments": [
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      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
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      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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      [
        "MSB"
      ],
      [
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      [
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        "MSB"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_s8]_z",
    "arguments": [
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      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
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      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "MSB"
      ],
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        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B[*]|Ztied3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "op3": {
        "register": "Zop3.B|Ztied3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ],
      [
        "MOVPRFX",
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmsb[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MSB"
      ],
      [
        "MSB"
      ],
      [
        "MLS"
      ],
      [
        "MOVPRFX",
        "MSB"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
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      "value": "svuint16_t"
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        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
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        "register": "Zop3.H"
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        "register": "Pg.H"
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        "MSB"
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        "MSB"
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      [
        "MOVPRFX",
        "MLS"
      ]
    ]
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    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
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      "value": "svuint32_t"
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
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      "op3": {
        "register": "Zop3.S"
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      "pg": {
        "register": "Pg.S"
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        "MSB"
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    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
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      "value": "svuint32_t"
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
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      "op3": {
        "register": "Zop3.S|Ztied3.S"
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        "register": "Pg.S"
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        "MSB"
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  {
    "SIMD_ISA": "SVE",
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      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
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      "value": "svuint32_t"
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      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
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        "MLS"
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
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      "value": "svuint64_t"
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        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
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      "op3": {
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      [
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        "MSB"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op2",
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        "register": "Zop1.D|Ztied1.D"
      },
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        "register": "Zop3.D|Ztied3.D"
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        "MSB"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
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      "value": "svuint64_t"
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      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
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      "op3": {
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      "pg": {
        "register": "Pg.D"
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        "MLS"
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      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
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      "value": "svuint8_t"
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      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
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      "pg": {
        "register": "Pg.B"
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        "MSB"
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  {
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      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
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      "value": "svuint8_t"
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      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
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      "op3": {
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      "pg": {
        "register": "Pg.B"
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        "MSB"
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  {
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      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
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      "value": "svuint8_t"
    },
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      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
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      "pg": {
        "register": "Pg.B"
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        "MSB"
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      [
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        "MLS"
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    "SIMD_ISA": "SVE",
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      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
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      "value": "svfloat16_t"
    },
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
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        "register": "Zop2.H"
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        "register": "Pg.H"
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        "FMUL"
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      "svfloat16_t op1",
      "svfloat16_t op2"
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      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H|Ztied2.H"
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        "FMUL"
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    "SIMD_ISA": "SVE",
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      "svfloat16_t op1",
      "svfloat16_t op2"
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        "register": "Zop1.H"
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        "FMUL"
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        "FMUL"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
      "svfloat32_t op2"
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      "value": "svfloat32_t"
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      "op1": {
        "register": "Zop1.S|Ztied1.S"
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        "register": "Zop2.S"
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        "FMUL"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat32_t op1",
      "svfloat32_t op2"
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        "register": "Zop1.S|Ztied1.S"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop1.S"
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      "svfloat64_t op1",
      "svfloat64_t op2"
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        "FMUL"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat64_t op1",
      "svfloat64_t op2"
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    "Arguments_Preparation": {
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        "register": "Zop1.D|Ztied1.D"
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        "register": "Zop2.D|Ztied2.D"
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        "FMUL"
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      "svfloat16_t op1",
      "float16_t op2"
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        "register": "Ztied1.H"
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      "svfloat16_t op1",
      "float16_t op2"
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        "register": "Zop1.H|Ztied1.H"
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      "svfloat16_t op1",
      "float16_t op2"
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        "register": "Zop1.H"
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        "FMUL"
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      "float32_t op2"
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        "register": "Ztied1.S"
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      "svfloat32_t op1",
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        "register": "Zop1.S|Ztied1.S"
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        "FMUL"
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  {
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      "svfloat64_t op1",
      "float64_t op2"
    ],
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        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
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      "pg": {
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    "instructions": [
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      [
        "FMUL"
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_f64]_x",
    "arguments": [
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      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
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      "pg": {
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    "instructions": [
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      ],
      [
        "FMUL"
      ],
      [
        "FMUL"
      ],
      [
        "FMUL"
      ],
      [
        "MOVPRFX",
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMUL"
      ],
      [
        "MOVPRFX",
        "FMUL"
      ],
      [
        "MOVPRFX",
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ],
      [
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "MUL"
      ],
      [
        "MOVPRFX",
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul_lane[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul_lane[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmul_lane[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmul_lane[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULH"
      ],
      [
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SMULH"
      ],
      [
        "MOVPRFX",
        "SMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULH"
      ],
      [
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulh[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UMULH"
      ],
      [
        "MOVPRFX",
        "UMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb_lane[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb_lane[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb_lane[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullb_lane[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt_lane[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt_lane[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt_lane[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svmullt_lane[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ],
      [
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svmulx[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FMULX"
      ],
      [
        "MOVPRFX",
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnand[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NAND"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "svuint16_t op3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "svuint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnbsl[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NBSL"
      ],
      [
        "MOVPRFX",
        "NBSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ],
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ],
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svneg[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmad[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnmatch[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NMATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnmatch[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NMATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnmatch[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NMATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svnmatch[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NMATCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S|Ztied3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "svfloat32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D|Ztied3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "svfloat64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLA"
      ],
      [
        "FNMAD"
      ],
      [
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmla[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMLA"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ],
      [
        "MOVPRFX",
        "FNMAD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmls[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLS"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmls[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "svfloat16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H|Ztied3.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMLS"
      ],
      [
        "FNMSB"
      ],
      [
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmls[_f16]_z",
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      "svbool_t pg",
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        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "op3": {
        "register": "Zop3.H[*]|Ztied3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMSB"
      ],
      [
        "FNMSB"
      ],
      [
        "FNMLS"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2",
      "float16_t op3"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "op3": {
        "register": "Zop3.S[*]|Ztied3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMSB"
      ],
      [
        "FNMSB"
      ],
      [
        "FNMLS"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2",
      "float32_t op3"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "op3": {
        "register": "Zop3.D[*]|Ztied3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "FNMSB"
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      [
        "FNMSB"
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      [
        "FNMLS"
      ],
      [
        "MOVPRFX",
        "FNMSB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnmsb[_n_f64]_z",
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      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2",
      "float64_t op3"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "FNMSB"
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      [
        "MOVPRFX",
        "FNMSB"
      ],
      [
        "MOVPRFX",
        "FNMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnor[_b]_z",
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      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
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      "A64"
    ],
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        "NOR"
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_b]_z",
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      "svbool_t pg",
      "svbool_t op"
    ],
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      "value": "svbool_t"
    },
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      "op": {
        "register": "Pop.B"
      },
      "pg": {
        "register": "Pg.B"
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    },
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      "A64"
    ],
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      [
        "EOR"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
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    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOT"
      ],
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svnot[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "NOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorn[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_b]_z",
    "arguments": [
      "svbool_t pg",
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ],
      [
        "ORR"
      ],
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorr[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "ORR"
      ],
      [
        "MOVPRFX",
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svorv[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ORV"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpfalse[_b]",
    "arguments": [],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PFALSE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpfirst[_b]",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ptied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PFIRST"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmul[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmul[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullb_pair[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpmullt_pair[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpnext_b16",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ptied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PNEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpnext_b32",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ptied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PNEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpnext_b64",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ptied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PNEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svpnext_b8",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Ptied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PNEXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather[_u32base]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather[_u32base]_offset",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather[_u64base]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather[_u64base]_offset",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather_[s32]offset",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint32_t offsets",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather_[s64]offset",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint64_t offsets",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather_[u32]offset",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint32_t offsets",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_gather_[u64]offset",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint64_t offsets",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfb_vnum",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "int64_t vnum",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFB"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ],
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather[_u32base]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather[_u32base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather[_u64base]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather[_u64base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather_[s32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather_[s64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather_[u32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_gather_[u64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfd_vnum",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "int64_t vnum",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFD"
      ],
      [
        "PRFD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ],
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather[_u32base]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather[_u32base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather[_u64base]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather[_u64base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather_[s32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather_[s64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather_[u32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_gather_[u64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfh_vnum",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "int64_t vnum",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFH"
      ],
      [
        "PRFH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ],
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather[_u32base]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather[_u32base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather[_u64base]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather[_u64base]_index",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ],
      [
        "PRFB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather_[s32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather_[s64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather_[u32]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint32_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_gather_[u64]index",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "svuint64_t indices",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svprfw_vnum",
    "arguments": [
      "svbool_t pg",
      "const void *base",
      "int64_t vnum",
      "enum svprfop op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PRFW"
      ],
      [
        "PRFW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpsel_lane_b16",
    "arguments": [
      "svbool_t pn",
      "svbool_t pm",
      "uint32_t idx"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "index": "[Wreg1, imm1]"
      },
      "pm": {
        "register": "Preg3"
      },
      "pn": {
        "register": "Preg2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PSEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpsel_lane_b32",
    "arguments": [
      "svbool_t pn",
      "svbool_t pm",
      "uint32_t idx"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "index": "[Wreg1, imm1]"
      },
      "pm": {
        "register": "Preg3"
      },
      "pn": {
        "register": "Preg2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PSEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpsel_lane_b64",
    "arguments": [
      "svbool_t pn",
      "svbool_t pm",
      "uint32_t idx"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "index": "[Wreg1, imm1]"
      },
      "pm": {
        "register": "Preg3"
      },
      "pn": {
        "register": "Preg2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PSEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svpsel_lane_b8",
    "arguments": [
      "svbool_t pn",
      "svbool_t pm",
      "uint32_t idx"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "index": "[Wreg1, imm1]"
      },
      "pm": {
        "register": "Preg3"
      },
      "pn": {
        "register": "Preg2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PSEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptest_any",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "bool"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptest_first",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "bool"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptest_last",
    "arguments": [
      "svbool_t pg",
      "svbool_t op"
    ],
    "return_type": {
      "value": "bool"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_b16",
    "arguments": [],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_b32",
    "arguments": [],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_b64",
    "arguments": [],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_b8",
    "arguments": [],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_pat_b16",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_pat_b32",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_pat_b64",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svptrue_pat_b8",
    "arguments": [
      "enum svpattern pattern"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PTRUE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ],
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqabs[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SQADD"
      ],
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQADD"
      ],
      [
        "MOVPRFX",
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqadd[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "UQADD"
      ],
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqadd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQADD"
      ],
      [
        "MOVPRFX",
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcadd[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCADD"
      ],
      [
        "MOVPRFX",
        "SQCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcadd[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCADD"
      ],
      [
        "MOVPRFX",
        "SQCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcadd[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCADD"
      ],
      [
        "MOVPRFX",
        "SQCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcadd[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCADD"
      ],
      [
        "MOVPRFX",
        "SQCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcvtn_s16[_s32_x2]",
    "arguments": [
      "svint32x2_t zn"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCVTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcvtn_u16[_s32_x2]",
    "arguments": [
      "svint32x2_t zn"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQCVTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqcvtn_u16[_u32_x2]",
    "arguments": [
      "svuint32x2_t zn"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQCVTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecb_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_s64]",
    "arguments": [
      "svint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ],
      [
        "MOVPRFX",
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd[_u64]",
    "arguments": [
      "svuint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ],
      [
        "MOVPRFX",
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_s64]",
    "arguments": [
      "svint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECD"
      ],
      [
        "MOVPRFX",
        "SQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecd_pat[_u64]",
    "arguments": [
      "svuint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECD"
      ],
      [
        "MOVPRFX",
        "UQDECD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_s16]",
    "arguments": [
      "svint16_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ],
      [
        "MOVPRFX",
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech[_u16]",
    "arguments": [
      "svuint16_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ],
      [
        "MOVPRFX",
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_s16]",
    "arguments": [
      "svint16_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECH"
      ],
      [
        "MOVPRFX",
        "SQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdech_pat[_u16]",
    "arguments": [
      "svuint16_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECH"
      ],
      [
        "MOVPRFX",
        "UQDECH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s32]_b16",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s32]_b32",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s32]_b64",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s32]_b8",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s64]_b16",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s64]_b32",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s64]_b64",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_s64]_b8",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u32]_b16",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u32]_b32",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u32]_b64",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u32]_b8",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u64]_b16",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u64]_b32",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u64]_b64",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_n_u64]_b8",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_s16]",
    "arguments": [
      "svint16_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ],
      [
        "MOVPRFX",
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_s32]",
    "arguments": [
      "svint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ],
      [
        "MOVPRFX",
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_s64]",
    "arguments": [
      "svint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECP"
      ],
      [
        "MOVPRFX",
        "SQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_u16]",
    "arguments": [
      "svuint16_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ],
      [
        "MOVPRFX",
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_u32]",
    "arguments": [
      "svuint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ],
      [
        "MOVPRFX",
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecp[_u64]",
    "arguments": [
      "svuint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECP"
      ],
      [
        "MOVPRFX",
        "UQDECP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_s32]",
    "arguments": [
      "svint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ],
      [
        "MOVPRFX",
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw[_u32]",
    "arguments": [
      "svuint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ],
      [
        "MOVPRFX",
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_s32]",
    "arguments": [
      "svint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDECW"
      ],
      [
        "MOVPRFX",
        "SQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqdecw_pat[_u32]",
    "arguments": [
      "svuint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQDECW"
      ],
      [
        "MOVPRFX",
        "UQDECW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalb_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALB"
      ],
      [
        "MOVPRFX",
        "SQDMLALB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalbt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALBT"
      ],
      [
        "MOVPRFX",
        "SQDMLALBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlalt_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLALT"
      ],
      [
        "MOVPRFX",
        "SQDMLALT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslb_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLB"
      ],
      [
        "MOVPRFX",
        "SQDMLSLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslbt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLBT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmlslt_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSLT"
      ],
      [
        "MOVPRFX",
        "SQDMLSLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmulh_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb_lane[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullb_lane[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt_lane[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqdmullt_lane[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincb_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_s64]",
    "arguments": [
      "svint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ],
      [
        "MOVPRFX",
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd[_u64]",
    "arguments": [
      "svuint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ],
      [
        "MOVPRFX",
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_s64]",
    "arguments": [
      "svint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCD"
      ],
      [
        "MOVPRFX",
        "SQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincd_pat[_u64]",
    "arguments": [
      "svuint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.D|Ztied.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCD"
      ],
      [
        "MOVPRFX",
        "UQINCD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_s16]",
    "arguments": [
      "svint16_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ],
      [
        "MOVPRFX",
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch[_u16]",
    "arguments": [
      "svuint16_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ],
      [
        "MOVPRFX",
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_s16]",
    "arguments": [
      "svint16_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCH"
      ],
      [
        "MOVPRFX",
        "SQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqinch_pat[_u16]",
    "arguments": [
      "svuint16_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.H|Ztied.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCH"
      ],
      [
        "MOVPRFX",
        "UQINCH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s32]_b16",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s32]_b32",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s32]_b64",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s32]_b8",
    "arguments": [
      "int32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s64]_b16",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s64]_b32",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s64]_b64",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_s64]_b8",
    "arguments": [
      "int64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u32]_b16",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u32]_b32",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u32]_b64",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u32]_b8",
    "arguments": [
      "uint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Wtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u64]_b16",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u64]_b32",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u64]_b64",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_n_u64]_b8",
    "arguments": [
      "uint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Xtied"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_s16]",
    "arguments": [
      "svint16_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ],
      [
        "MOVPRFX",
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_s32]",
    "arguments": [
      "svint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ],
      [
        "MOVPRFX",
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_s64]",
    "arguments": [
      "svint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCP"
      ],
      [
        "MOVPRFX",
        "SQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_u16]",
    "arguments": [
      "svuint16_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ],
      [
        "MOVPRFX",
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_u32]",
    "arguments": [
      "svuint32_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ],
      [
        "MOVPRFX",
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincp[_u64]",
    "arguments": [
      "svuint64_t op",
      "svbool_t pg"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCP"
      ],
      [
        "MOVPRFX",
        "UQINCP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_n_s32]",
    "arguments": [
      "int32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_n_s64]",
    "arguments": [
      "int64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_n_u32]",
    "arguments": [
      "uint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_n_u64]",
    "arguments": [
      "uint64_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_s32]",
    "arguments": [
      "svint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ],
      [
        "MOVPRFX",
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw[_u32]",
    "arguments": [
      "svuint32_t op",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ],
      [
        "MOVPRFX",
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_n_s32]",
    "arguments": [
      "int32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_n_s64]",
    "arguments": [
      "int64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_n_u32]",
    "arguments": [
      "uint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Wtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_n_u64]",
    "arguments": [
      "uint64_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Xtied"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_s32]",
    "arguments": [
      "svint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQINCW"
      ],
      [
        "MOVPRFX",
        "SQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqincw_pat[_u32]",
    "arguments": [
      "svuint32_t op",
      "enum svpattern pattern",
      "uint64_t imm_factor"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm_factor": {
        "minimum": 1,
        "maximum": 16
      },
      "op": {
        "register": "Zop.S|Ztied.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQINCW"
      ],
      [
        "MOVPRFX",
        "UQINCW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ],
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqneg[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdcmlah_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index",
      "uint64_t imm_rotation"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDCMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDCMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlah_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ],
      [
        "MOVPRFX",
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "int16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "int32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "int64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "svint16_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "op3": {
        "register": "Zop3.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "svint32_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmlsh_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "svint64_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ],
      [
        "MOVPRFX",
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh_lane[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrdmulh_lane[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 1
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SRSHR"
      ],
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "URSHR"
      ],
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ],
      [
        "SQRSHLR"
      ],
      [
        "MOVPRFX",
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQRSHL"
      ],
      [
        "MOVPRFX",
        "SQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ],
      [
        "UQRSHLR"
      ],
      [
        "MOVPRFX",
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshl[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQRSHL"
      ],
      [
        "MOVPRFX",
        "UQRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrn[_n]_s16[_s32_x2]",
    "arguments": [
      "svint32x2_t zn",
      "uint64_t imm"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm": {
        "immediate": "imm1"
      },
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrn[_n]_u16[_u32_x2]",
    "arguments": [
      "svuint32x2_t zn",
      "uint64_t imm"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm": {
        "immediate": "imm1"
      },
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrun[_n]_u16[_s32_x2]",
    "arguments": [
      "svint32x2_t zn",
      "uint64_t imm"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm": {
        "immediate": "imm1"
      },
      "zn": {
        "Z multi-vector": "{ Zreg2.S, Zreg3.S }"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunt[_n_s16]",
    "arguments": [
      "svuint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunt[_n_s32]",
    "arguments": [
      "svuint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqrshrunt[_n_s64]",
    "arguments": [
      "svuint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "ASR"
      ],
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "ASR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "LSR"
      ],
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "LSR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ],
      [
        "SQSHLR"
      ],
      [
        "MOVPRFX",
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHL"
      ],
      [
        "MOVPRFX",
        "SQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ],
      [
        "UQSHLR"
      ],
      [
        "MOVPRFX",
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshl[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSHL"
      ],
      [
        "MOVPRFX",
        "UQSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Zop1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHLU"
      ],
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshlu[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunt[_n_s16]",
    "arguments": [
      "svuint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunt[_n_s32]",
    "arguments": [
      "svuint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqshrunt[_n_s64]",
    "arguments": [
      "svuint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQADD"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ],
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUB"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svqsub[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ],
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsub[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUB"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUBR"
      ],
      [
        "SQSUB"
      ],
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SQSUBR"
      ],
      [
        "MOVPRFX",
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUBR"
      ],
      [
        "UQSUB"
      ],
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqsubr[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "UQSUBR"
      ],
      [
        "MOVPRFX",
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_s16]",
    "arguments": [
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_s32]",
    "arguments": [
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_s64]",
    "arguments": [
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_u16]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_u32]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnb[_u64]",
    "arguments": [
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtnt[_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunb[_s16]",
    "arguments": [
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunb[_s32]",
    "arguments": [
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunb[_s64]",
    "arguments": [
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunt[_s16]",
    "arguments": [
      "svuint8_t even",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunt[_s32]",
    "arguments": [
      "svuint16_t even",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svqxtunt[_s64]",
    "arguments": [
      "svuint32_t even",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svraddhnt[_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrax1[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RAX1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrax1[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RAX1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s16]_m",
    "arguments": [
      "svint16_t inactive",
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s8]_m",
    "arguments": [
      "svint8_t inactive",
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u16]_m",
    "arguments": [
      "svuint16_t inactive",
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u8]_m",
    "arguments": [
      "svuint8_t inactive",
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.B|Ztied.B"
      },
      "op": {
        "register": "Zop.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B|Ztied.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ],
      [
        "MOVPRFX",
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrbit[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op": {
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      "A64"
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  },
  {
    "SIMD_ISA": "SVE",
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      "value": "svuint8_t"
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    "Architectures": [
      "A64"
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_s32]",
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_s64]",
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  {
    "SIMD_ISA": "SVE",
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      "value": "svuint8_t"
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      "A64"
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_u16]",
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      "A64"
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_u32]",
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      "value": "svuint8_t"
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      "A64"
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_u64]",
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  {
    "SIMD_ISA": "SVE",
    "name": "svreinterpret_u8[_u8]",
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      "value": "svuint8_t"
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_f16]",
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        "register": "Zop.H"
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        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_f32]",
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        "register": "Zop.S"
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      "A64"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_f64]",
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        "register": "Zop.D"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_s16]",
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        "register": "Zop.H"
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      "A64"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop.S"
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      "A64"
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      [
        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_s64]",
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      "op": {
        "register": "Zop.D"
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      "A64"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "op": {
        "register": "Zop.B"
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      "A64"
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      [
        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_u16]",
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      "svuint16_t op"
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      "op": {
        "register": "Zop.H"
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    "Architectures": [
      "A64"
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      [
        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_u32]",
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      "value": "svuint32_t"
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      "op": {
        "register": "Zop.S"
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      "A64"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrev[_u64]",
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      "value": "svuint64_t"
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      "op": {
        "register": "Zop.D"
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      "A64"
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      [
        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svuint8_t"
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      "op": {
        "register": "Zop.B"
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    "Architectures": [
      "A64"
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      [
        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svbool_t"
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      "op": {
        "register": "Pop.H"
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      "A64"
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      [
        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svbool_t"
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      "op": {
        "register": "Pop.S"
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        "REV"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
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      "value": "svbool_t"
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      "op": {
        "register": "Pop.D"
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        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
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        "register": "Pop.B"
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        "REV"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "inactive": {
        "register": "Zinactive.H|Ztied.H"
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        "register": "Zop.H"
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        "register": "Pg.H"
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        "REVB"
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      [
        "MOVPRFX",
        "REVB"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_s16]_x",
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      "op": {
        "register": "Zop.H|Ztied.H"
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        "REVB"
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      [
        "MOVPRFX",
        "REVB"
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_s16]_z",
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        "register": "Zop.H"
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        "MOVPRFX",
        "REVB"
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    "SIMD_ISA": "SVE",
    "name": "svrevb[_s32]_m",
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        "register": "Zinactive.S|Ztied.S"
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        "REVB"
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        "MOVPRFX",
        "REVB"
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_s32]_x",
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        "register": "Zop.S|Ztied.S"
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        "REVB"
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        "MOVPRFX",
        "REVB"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop.S"
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        "MOVPRFX",
        "REVB"
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    "SIMD_ISA": "SVE",
    "name": "svrevb[_s64]_m",
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      "svbool_t pg",
      "svint64_t op"
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    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
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        "register": "Pg.D"
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    "instructions": [
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        "REVB"
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      [
        "MOVPRFX",
        "REVB"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_s64]_x",
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      "svint64_t op"
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      "value": "svint64_t"
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    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
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      "pg": {
        "register": "Pg.D"
      }
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    "Architectures": [
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    ],
    "instructions": [
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        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_s64]_z",
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      "svint64_t op"
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        "register": "Zop.D"
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "MOVPRFX",
        "REVB"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u16]_m",
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      "svbool_t pg",
      "svuint16_t op"
    ],
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      "value": "svuint16_t"
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    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
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      "pg": {
        "register": "Pg.H"
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    "Architectures": [
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    "instructions": [
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        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u16]_x",
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      "svuint16_t op"
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      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
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    "Architectures": [
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    ],
    "instructions": [
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        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u16]_z",
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      "svuint16_t op"
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      "value": "svuint16_t"
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      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
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    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u32]_m",
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      "svbool_t pg",
      "svuint32_t op"
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      "value": "svuint32_t"
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    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
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      "pg": {
        "register": "Pg.S"
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    "Architectures": [
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    ],
    "instructions": [
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        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u32]_x",
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      "svbool_t pg",
      "svuint32_t op"
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
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      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
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    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u64]_m",
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      "svbool_t pg",
      "svuint64_t op"
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      "value": "svuint64_t"
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    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
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    "Architectures": [
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    "instructions": [
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        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "REVB"
      ],
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevb[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f16]_m",
    "arguments": [
      "svfloat16_t zd",
      "svbool_t pg",
      "svfloat16_t zn"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t zn"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t zn"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f32]_m",
    "arguments": [
      "svfloat32_t zd",
      "svbool_t pg",
      "svfloat32_t zn"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t zn"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t zn"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f64]_m",
    "arguments": [
      "svfloat64_t zd",
      "svbool_t pg",
      "svfloat64_t zn"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t zn"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t zn"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s16]_m",
    "arguments": [
      "svint16_t zd",
      "svbool_t pg",
      "svint16_t zn"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t zn"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t zn"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s32]_m",
    "arguments": [
      "svint32_t zd",
      "svbool_t pg",
      "svint32_t zn"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t zn"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t zn"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s64]_m",
    "arguments": [
      "svint64_t zd",
      "svbool_t pg",
      "svint64_t zn"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t zn"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t zn"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s8]_m",
    "arguments": [
      "svint8_t zd",
      "svbool_t pg",
      "svint8_t zn"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t zn"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t zn"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u16]_m",
    "arguments": [
      "svuint16_t zd",
      "svbool_t pg",
      "svuint16_t zn"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t zn"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t zn"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u32]_m",
    "arguments": [
      "svuint32_t zd",
      "svbool_t pg",
      "svuint32_t zn"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t zn"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t zn"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u64]_m",
    "arguments": [
      "svuint64_t zd",
      "svbool_t pg",
      "svuint64_t zn"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t zn"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t zn"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u8]_m",
    "arguments": [
      "svuint8_t zd",
      "svbool_t pg",
      "svuint8_t zn"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zd": {
        "register": "Zreg1.Q"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t zn"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV",
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrevd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t zn"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "pg": {
        "register": "Preg1"
      },
      "zn": {
        "register": "Zreg2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s32]_m",
    "arguments": [
      "svint32_t inactive",
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVH"
      ],
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevh[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVH"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_s64]_m",
    "arguments": [
      "svint64_t inactive",
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVW"
      ],
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVW"
      ],
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_u64]_m",
    "arguments": [
      "svuint64_t inactive",
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVW"
      ],
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "REVW"
      ],
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrevw[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "REVW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ],
      [
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRHADD"
      ],
      [
        "MOVPRFX",
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URHADD"
      ],
      [
        "URHADD"
      ],
      [
        "MOVPRFX",
        "URHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrhadd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
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    "instructions": [
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        "FRINTN"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintn[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTN"
      ],
      [
        "MOVPRFX",
        "FRINTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintn[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTP"
      ],
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTP"
      ],
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
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      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTP"
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      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTP"
      ],
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
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      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "FRINTP"
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      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTP"
      ],
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintp[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTP"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
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      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ],
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ],
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ],
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ],
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ],
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintx[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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    ],
    "instructions": [
      [
        "FRINTZ"
      ],
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrintz[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "MOVPRFX",
        "FRINTZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "LSL"
      ],
      [
        "SRSHR"
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      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
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    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
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        "register": "Zop2.H[*]|Ztied2.H[*]"
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      "pg": {
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      }
    },
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    "instructions": [
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        "SRSHR"
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      [
        "SRSHLR"
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        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
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      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
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        "MOVPRFX",
        "LSL"
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      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s32]_m",
    "arguments": [
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      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
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        "register": "Pg.S"
      }
    },
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    ],
    "instructions": [
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        "LSL"
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      [
        "SRSHR"
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      [
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      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "SRSHR"
      ],
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "SRSHR"
      ],
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "SRSHR"
      ],
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "SRSHR"
      ],
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "SRSHR"
      ],
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LSL"
      ],
      [
        "URSHR"
      ],
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "LSL"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ],
      [
        "SRSHLR"
      ],
      [
        "MOVPRFX",
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHL"
      ],
      [
        "MOVPRFX",
        "SRSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ],
      [
        "URSHLR"
      ],
      [
        "MOVPRFX",
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshl[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHL"
      ],
      [
        "MOVPRFX",
        "URSHLR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ],
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ],
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrshrnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrte[_f16]",
    "arguments": [
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrte[_f32]",
    "arguments": [
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrte[_f64]",
    "arguments": [
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsqrte[_u32]_m",
    "arguments": [
      "svuint32_t inactive",
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ],
      [
        "MOVPRFX",
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsqrte[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ],
      [
        "MOVPRFX",
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsqrte[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrts[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrts[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svrsqrts[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ],
      [
        "MOVPRFX",
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ],
      [
        "MOVPRFX",
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ],
      [
        "MOVPRFX",
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ],
      [
        "MOVPRFX",
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ],
      [
        "MOVPRFX",
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ],
      [
        "MOVPRFX",
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ],
      [
        "MOVPRFX",
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsra[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ],
      [
        "MOVPRFX",
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svrsubhnt[_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsbclb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "op3": {
        "register": "Zop3.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SBCLB"
      ],
      [
        "MOVPRFX",
        "SBCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsbclb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t op3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "op3": {
        "register": "Zop3.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SBCLB"
      ],
      [
        "MOVPRFX",
        "SBCLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsbclb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "svuint32_t op3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
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    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsel[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsel[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsel[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsel[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SEL"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_f16]",
    "arguments": [
      "svfloat16x2_t tuple",
      "uint64_t imm_index",
      "svfloat16_t x"
    ],
    "return_type": {
      "value": "svfloat16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_f32]",
    "arguments": [
      "svfloat32x2_t tuple",
      "uint64_t imm_index",
      "svfloat32_t x"
    ],
    "return_type": {
      "value": "svfloat32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_f64]",
    "arguments": [
      "svfloat64x2_t tuple",
      "uint64_t imm_index",
      "svfloat64_t x"
    ],
    "return_type": {
      "value": "svfloat64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_s16]",
    "arguments": [
      "svint16x2_t tuple",
      "uint64_t imm_index",
      "svint16_t x"
    ],
    "return_type": {
      "value": "svint16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_s32]",
    "arguments": [
      "svint32x2_t tuple",
      "uint64_t imm_index",
      "svint32_t x"
    ],
    "return_type": {
      "value": "svint32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_s64]",
    "arguments": [
      "svint64x2_t tuple",
      "uint64_t imm_index",
      "svint64_t x"
    ],
    "return_type": {
      "value": "svint64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_s8]",
    "arguments": [
      "svint8x2_t tuple",
      "uint64_t imm_index",
      "svint8_t x"
    ],
    "return_type": {
      "value": "svint8x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_u16]",
    "arguments": [
      "svuint16x2_t tuple",
      "uint64_t imm_index",
      "svuint16_t x"
    ],
    "return_type": {
      "value": "svuint16x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_u32]",
    "arguments": [
      "svuint32x2_t tuple",
      "uint64_t imm_index",
      "svuint32_t x"
    ],
    "return_type": {
      "value": "svuint32x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_u64]",
    "arguments": [
      "svuint64x2_t tuple",
      "uint64_t imm_index",
      "svuint64_t x"
    ],
    "return_type": {
      "value": "svuint64x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset2[_u8]",
    "arguments": [
      "svuint8x2_t tuple",
      "uint64_t imm_index",
      "svuint8_t x"
    ],
    "return_type": {
      "value": "svuint8x2_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_f16]",
    "arguments": [
      "svfloat16x3_t tuple",
      "uint64_t imm_index",
      "svfloat16_t x"
    ],
    "return_type": {
      "value": "svfloat16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_f32]",
    "arguments": [
      "svfloat32x3_t tuple",
      "uint64_t imm_index",
      "svfloat32_t x"
    ],
    "return_type": {
      "value": "svfloat32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_f64]",
    "arguments": [
      "svfloat64x3_t tuple",
      "uint64_t imm_index",
      "svfloat64_t x"
    ],
    "return_type": {
      "value": "svfloat64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_s16]",
    "arguments": [
      "svint16x3_t tuple",
      "uint64_t imm_index",
      "svint16_t x"
    ],
    "return_type": {
      "value": "svint16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_s32]",
    "arguments": [
      "svint32x3_t tuple",
      "uint64_t imm_index",
      "svint32_t x"
    ],
    "return_type": {
      "value": "svint32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_s64]",
    "arguments": [
      "svint64x3_t tuple",
      "uint64_t imm_index",
      "svint64_t x"
    ],
    "return_type": {
      "value": "svint64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_s8]",
    "arguments": [
      "svint8x3_t tuple",
      "uint64_t imm_index",
      "svint8_t x"
    ],
    "return_type": {
      "value": "svint8x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_u16]",
    "arguments": [
      "svuint16x3_t tuple",
      "uint64_t imm_index",
      "svuint16_t x"
    ],
    "return_type": {
      "value": "svuint16x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_u32]",
    "arguments": [
      "svuint32x3_t tuple",
      "uint64_t imm_index",
      "svuint32_t x"
    ],
    "return_type": {
      "value": "svuint32x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_u64]",
    "arguments": [
      "svuint64x3_t tuple",
      "uint64_t imm_index",
      "svuint64_t x"
    ],
    "return_type": {
      "value": "svuint64x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset3[_u8]",
    "arguments": [
      "svuint8x3_t tuple",
      "uint64_t imm_index",
      "svuint8_t x"
    ],
    "return_type": {
      "value": "svuint8x3_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_f16]",
    "arguments": [
      "svfloat16x4_t tuple",
      "uint64_t imm_index",
      "svfloat16_t x"
    ],
    "return_type": {
      "value": "svfloat16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_f32]",
    "arguments": [
      "svfloat32x4_t tuple",
      "uint64_t imm_index",
      "svfloat32_t x"
    ],
    "return_type": {
      "value": "svfloat32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_f64]",
    "arguments": [
      "svfloat64x4_t tuple",
      "uint64_t imm_index",
      "svfloat64_t x"
    ],
    "return_type": {
      "value": "svfloat64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_s16]",
    "arguments": [
      "svint16x4_t tuple",
      "uint64_t imm_index",
      "svint16_t x"
    ],
    "return_type": {
      "value": "svint16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_s32]",
    "arguments": [
      "svint32x4_t tuple",
      "uint64_t imm_index",
      "svint32_t x"
    ],
    "return_type": {
      "value": "svint32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_s64]",
    "arguments": [
      "svint64x4_t tuple",
      "uint64_t imm_index",
      "svint64_t x"
    ],
    "return_type": {
      "value": "svint64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_s8]",
    "arguments": [
      "svint8x4_t tuple",
      "uint64_t imm_index",
      "svint8_t x"
    ],
    "return_type": {
      "value": "svint8x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_u16]",
    "arguments": [
      "svuint16x4_t tuple",
      "uint64_t imm_index",
      "svuint16_t x"
    ],
    "return_type": {
      "value": "svuint16x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_u32]",
    "arguments": [
      "svuint32x4_t tuple",
      "uint64_t imm_index",
      "svuint32_t x"
    ],
    "return_type": {
      "value": "svuint32x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_u64]",
    "arguments": [
      "svuint64x4_t tuple",
      "uint64_t imm_index",
      "svuint64_t x"
    ],
    "return_type": {
      "value": "svuint64x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svset4[_u8]",
    "arguments": [
      "svuint8x4_t tuple",
      "uint64_t imm_index",
      "svuint8_t x"
    ],
    "return_type": {
      "value": "svuint8x4_t"
    },
    "Architectures": [
      "A64"
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsetffr",
    "arguments": [],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {},
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SETFFR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Zop1.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshllt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svshrnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t imm2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "imm2": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHRNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 15
      },
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 31
      },
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 63
      },
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsli[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 0,
        "maximum": 7
      },
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsm4e[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM4E"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsm4ekey[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM4EKEY"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_f16]",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_f32]",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_f64]",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_s16]",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_s32]",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_s64]",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_s8]",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_u16]",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsplice[_u8]",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SPLICE"
      ],
      [
        "MOVPRFX",
        "SPLICE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ],
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ],
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsqadd[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f16]_m",
    "arguments": [
      "svfloat16_t inactive",
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.H|Ztied.H"
      },
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H|Ztied.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f32]_m",
    "arguments": [
      "svfloat32_t inactive",
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.S|Ztied.S"
      },
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S|Ztied.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f64]_m",
    "arguments": [
      "svfloat64_t inactive",
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "inactive": {
        "register": "Zinactive.D|Ztied.D"
      },
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D|Ztied.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ],
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsqrt[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ],
      [
        "MOVPRFX",
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ],
      [
        "MOVPRFX",
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ],
      [
        "MOVPRFX",
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ],
      [
        "MOVPRFX",
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ],
      [
        "MOVPRFX",
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ],
      [
        "MOVPRFX",
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ],
      [
        "MOVPRFX",
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsra[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ],
      [
        "MOVPRFX",
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsri[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base]_index[_f32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base]_index[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base]_index[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base]_offset[_f32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base]_offset[_s32]",
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      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svint32_t data"
    ],
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      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svuint32_t data"
    ],
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      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "svuint32_t bases",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
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    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u32base_u32]",
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      "svbool_t pg",
      "svuint32_t bases",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_index[_f64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
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      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_index[_s64]",
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      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svint64_t data"
    ],
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      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_index[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 8": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_offset[_f64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svfloat64_t data"
    ],
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      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    "instructions": [
      [
        "ST1D"
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      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base_f64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
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    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[s32]index[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svint32_t indices",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
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    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "data": {
        "register": "Zdata.S"
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      "indices": {
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      "pg": {
        "register": "Pg.S"
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    "Architectures": [
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    "instructions": [
      [
        "ST1W"
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  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[s32]index[_s32]",
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      "svbool_t pg",
      "int32_t *base",
      "svint32_t indices",
      "svint32_t data"
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    "return_type": {
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    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "data": {
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      "indices": {
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      "pg": {
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    "instructions": [
      [
        "ST1W"
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  {
    "SIMD_ISA": "SVE",
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      "uint32_t *base",
      "svint32_t indices",
      "svuint32_t data"
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    "return_type": {
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    "Arguments_Preparation": {
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      "data": {
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      "pg": {
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    "instructions": [
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        "ST1W"
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "float32_t *base",
      "svint32_t offsets",
      "svfloat32_t data"
    ],
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    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
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      "data": {
        "register": "Zdata.S"
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      "offsets": {
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      "pg": {
        "register": "Pg.S"
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    "instructions": [
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        "ST1W"
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  {
    "SIMD_ISA": "SVE",
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      "int32_t *base",
      "svint32_t offsets",
      "svint32_t data"
    ],
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    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
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      "pg": {
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    },
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    "instructions": [
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        "ST1W"
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  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "uint32_t *base",
      "svint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
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      "offsets": {
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      },
      "pg": {
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    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[s64]index[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svint64_t indices",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
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      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    "instructions": [
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        "ST1D"
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  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[s64]index[_s64]",
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      "svbool_t pg",
      "int64_t *base",
      "svint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
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      },
      "pg": {
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    "Architectures": [
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    ],
    "instructions": [
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        "ST1D"
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  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[s64]index[_u64]",
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      "svbool_t pg",
      "uint64_t *base",
      "svint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
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    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
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    "SIMD_ISA": "SVE",
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      "float64_t *base",
      "svint64_t offsets",
      "svfloat64_t data"
    ],
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "data": {
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    "instructions": [
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        "ST1D"
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  {
    "SIMD_ISA": "SVE",
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      "int64_t *base",
      "svint64_t offsets",
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    ],
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    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
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      "offsets": {
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  {
    "SIMD_ISA": "SVE",
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      "svint64_t offsets",
      "svuint64_t data"
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    },
    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "data": {
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      "offsets": {
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      "pg": {
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    "instructions": [
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        "ST1D"
      ]
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  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t pg",
      "float32_t *base",
      "svuint32_t indices",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
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    "Arguments_Preparation": {
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        "register": "Xbase"
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      "data": {
        "register": "Zdata.S"
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      "indices": {
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      }
    },
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    ],
    "instructions": [
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        "ST1W"
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    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u32]index[_s32]",
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      "svbool_t pg",
      "int32_t *base",
      "svuint32_t indices",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
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      "pg": {
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    ],
    "instructions": [
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        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u32]index[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32_t indices",
      "svuint32_t data"
    ],
    "return_type": {
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    "Arguments_Preparation": {
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        "register": "Xbase"
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      "data": {
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      "indices": {
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      "pg": {
        "register": "Pg.S"
      }
    },
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    ],
    "instructions": [
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        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u32]offset[_f32]",
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      "svbool_t pg",
      "float32_t *base",
      "svuint32_t offsets",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svuint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]index[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svuint64_t indices",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svuint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]offset[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svuint64_t offsets",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "int64_t vnum",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "int64_t vnum",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "int64_t vnum",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "int64_t vnum",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "int64_t vnum",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1D"
      ],
      [
        "ST1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_s16]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_s32]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u32base]_offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u32base]_offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u32base_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u32base_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[s32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[s32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svuint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1b_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1B"
      ],
      [
        "ST1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base]_index[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base]_index[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base]_offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base]_offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u32base_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base]_index[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base]_index[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s32]index[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint32_t indices",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s32]index[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint32_t indices",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u32]index[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint32_t indices",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u32]index[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint32_t indices",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "indices": {
        "register": "Zindices.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1h_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1H"
      ],
      [
        "ST1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base]_index[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base]_index[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[s64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[s64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svuint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices": {
        "register": "Zindices.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst1w_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1W"
      ],
      [
        "ST1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "svfloat16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svfloat32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svfloat64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svint64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint8x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B, Zdata1.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2B"
      ],
      [
        "ST2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint8x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B, Zdata1.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2B"
      ],
      [
        "ST2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "int64_t vnum",
      "svfloat16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "int64_t vnum",
      "svfloat32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "int64_t vnum",
      "svfloat64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "int64_t vnum",
      "svint64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint8x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B, Zdata1.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2B"
      ],
      [
        "ST2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint16x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2H"
      ],
      [
        "ST2H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint32x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S, Zdata1.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2W"
      ],
      [
        "ST2W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "int64_t vnum",
      "svuint64x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D, Zdata1.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2D"
      ],
      [
        "ST2D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst2_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint8x2_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B, Zdata1.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2B"
      ],
      [
        "ST2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "svfloat16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svfloat32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svfloat64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svint64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint8x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata2.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3B"
      ],
      [
        "ST3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint8x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata2.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3B"
      ],
      [
        "ST3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "int64_t vnum",
      "svfloat16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "int64_t vnum",
      "svfloat32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "int64_t vnum",
      "svfloat64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "int64_t vnum",
      "svint64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint8x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata2.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3B"
      ],
      [
        "ST3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint16x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata2.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3H"
      ],
      [
        "ST3H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint32x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata2.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3W"
      ],
      [
        "ST3W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "int64_t vnum",
      "svuint64x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata2.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3D"
      ],
      [
        "ST3D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst3_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint8x3_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata2.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3B"
      ],
      [
        "ST3B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "svfloat16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svfloat32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svfloat64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svint64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint8x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata3.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4B"
      ],
      [
        "ST4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint8x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata3.B}"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4B"
      ],
      [
        "ST4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "int64_t vnum",
      "svfloat16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "int64_t vnum",
      "svfloat32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "int64_t vnum",
      "svfloat64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "int64_t vnum",
      "svint64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint8x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata3.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4B"
      ],
      [
        "ST4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint16x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.H - Zdata3.H}"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4H"
      ],
      [
        "ST4H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint32x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.S - Zdata3.S}"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4W"
      ],
      [
        "ST4W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "int64_t vnum",
      "svuint64x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.D - Zdata3.D}"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4D"
      ],
      [
        "ST4D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svst4_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint8x4_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "{Zdata0.B - Zdata3.B}"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4B"
      ],
      [
        "ST4B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ],
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ],
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1_scatter[_u32base]_index[_f32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1_scatter[_u32base]_index[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1_scatter[_u32base]_index[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svuint32_t data"
    ],
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        "STNT1W"
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        "STNT1W"
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  {
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      },
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    "instructions": [
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        "STNT1W"
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  {
    "SIMD_ISA": "SVE2",
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        "register": "Zbases.S"
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    "instructions": [
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        "STNT1W"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
      "int64_t index",
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    "Arguments_Preparation": {
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        "register": "Zbases.D"
      },
      "data": {
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      "index * 8": {
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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    "Arguments_Preparation": {
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      "data": {
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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      "svuint64_t data"
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    "Arguments_Preparation": {
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        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
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      "pg": {
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
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      "pg": {
        "register": "Pg.D"
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
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      "pg": {
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "svuint64_t bases",
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      "value": "void"
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    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
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      "pg": {
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "data": {
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    "instructions": [
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        "STNT1D"
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  {
    "SIMD_ISA": "SVE2",
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      "data": {
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  {
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      "int64_t *base",
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    "Arguments_Preparation": {
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    "instructions": [
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  {
    "SIMD_ISA": "SVE2",
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      "uint64_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
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    "Arguments_Preparation": {
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        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_f16]",
    "arguments": [
      "svbool_t pg",
      "float16_t *base",
      "int64_t vnum",
      "svfloat16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_f32]",
    "arguments": [
      "svbool_t pg",
      "float32_t *base",
      "int64_t vnum",
      "svfloat32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_f64]",
    "arguments": [
      "svbool_t pg",
      "float64_t *base",
      "int64_t vnum",
      "svfloat64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_s16]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "int64_t vnum",
      "svint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_s32]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "int64_t vnum",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_s64]",
    "arguments": [
      "svbool_t pg",
      "int64_t *base",
      "int64_t vnum",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_s8]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "int64_t vnum",
      "svint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ],
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_u16]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "int64_t vnum",
      "svuint16_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.H"
      },
      "pg": {
        "register": "Pg.H"
      },
      "vnum * svcnth()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ],
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "int64_t vnum",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      },
      "vnum * svcntw()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ],
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint64_t *base",
      "int64_t vnum",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      },
      "vnum * svcntd()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1D"
      ],
      [
        "STNT1D"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svstnt1_vnum[_u8]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "int64_t vnum",
      "svuint8_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.B"
      },
      "pg": {
        "register": "Pg.B"
      },
      "vnum * svcntb()": {
        "register": "Xindex"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ],
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u32base]_offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u32base]_offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u32base_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u32base_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svuint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int8_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1b_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint8_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base]_index[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base]_index[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t index",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base]_offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base]_offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "int64_t offset",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base_s32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u32base_u32]",
    "arguments": [
      "svbool_t pg",
      "svuint32_t bases",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.S"
      },
      "data": {
        "register": "Zdata.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base]_index[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base]_index[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 2": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[s64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 2": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[s64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 2": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u32]offset[_s32]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint32_t offsets",
      "svint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u32]offset[_u32]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint32_t offsets",
      "svuint32_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.S"
      },
      "offsets": {
        "register": "Zoffsets.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 2": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 2": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int16_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1h_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint16_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base]_index[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base]_index[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t index",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "index * 4": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base]_offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base]_offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "int64_t offset",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offset": {
        "register": "Xoffset"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base_s64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter[_u64base_u64]",
    "arguments": [
      "svbool_t pg",
      "svuint64_t bases",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "bases": {
        "register": "Zbases.D"
      },
      "data": {
        "register": "Zdata.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[s64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 4": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[s64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 4": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[s64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[s64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[u64]index[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svuint64_t indices",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 4": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[u64]index[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint64_t indices",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "indices * 4": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[u64]offset[_s64]",
    "arguments": [
      "svbool_t pg",
      "int32_t *base",
      "svuint64_t offsets",
      "svint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svstnt1w_scatter_[u64]offset[_u64]",
    "arguments": [
      "svbool_t pg",
      "uint32_t *base",
      "svuint64_t offsets",
      "svuint64_t data"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "base": {
        "register": "Xbase"
      },
      "data": {
        "register": "Zdata.D"
      },
      "offsets": {
        "register": "Zoffsets.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STNT1W"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f16]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f16]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "float16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f32]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f32]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f32]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat32_t op1",
      "float32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f64]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f64]_x",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ],
      [
        "FADD"
      ],
      [
        "FSUB"
      ],
      [
        "FSUBR"
      ],
      [
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_f64]_z",
    "arguments": [
      "svbool_t pg",
      "svfloat64_t op1",
      "float64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FADD"
      ],
      [
        "MOVPRFX",
        "FSUB"
      ],
      [
        "MOVPRFX",
        "FSUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "ADD"
      ],
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsub[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUB"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_n_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_s16]",
    "arguments": [
      "svint8_t even",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_s32]",
    "arguments": [
      "svint16_t even",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_s64]",
    "arguments": [
      "svint32_t even",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_u16]",
    "arguments": [
      "svuint8_t even",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.B"
      },
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_u32]",
    "arguments": [
      "svuint16_t even",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.H"
      },
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubhnt[_u64]",
    "arguments": [
      "svuint32_t even",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "even": {
        "register": "Ztied.S"
      },
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublb[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublbt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLBT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_u16]",
    "arguments": [
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_u32]",
    "arguments": [
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_n_u64]",
    "arguments": [
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_u16]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_u32]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsublt[_u64]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_n_s16]",
    "arguments": [
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_n_s32]",
    "arguments": [
      "svint16_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_n_s64]",
    "arguments": [
      "svint32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_s16]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_s32]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubltb[_s64]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBLTB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_f16]_m",
    "arguments": [
      "svbool_t pg",
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUBR"
      ],
      [
        "MOVPRFX",
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      "svfloat16_t op1",
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      "value": "svfloat16_t"
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        "register": "Zop1.H|Ztied1.H"
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    "SIMD_ISA": "SVE",
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.S|Ztied1.S"
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        "register": "Zop1.S|Ztied1.S"
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        "register": "Zop1.D|Ztied1.D"
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        "register": "Zop1.B|Ztied1.B"
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        "register": "Zop2.B[*]"
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    "instructions": [
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    "SIMD_ISA": "SVE",
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      "svint8_t op1",
      "int8_t op2"
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      "value": "svint8_t"
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    "Arguments_Preparation": {
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        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
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    "instructions": [
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  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]|Ztied2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]|Ztied2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]|Ztied2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]|Ztied2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_n_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u16]_m",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u16]_x",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u16]_z",
    "arguments": [
      "svbool_t pg",
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u32]_m",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u32]_x",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u32]_z",
    "arguments": [
      "svbool_t pg",
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u64]_m",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u64]_x",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u64]_z",
    "arguments": [
      "svbool_t pg",
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u8]_m",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUBR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u8]_x",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBR"
      ],
      [
        "SUB"
      ],
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsubr[_u8]_z",
    "arguments": [
      "svbool_t pg",
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUBR"
      ],
      [
        "MOVPRFX",
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwb[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWB"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "int8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "int16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svsubwt[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBWT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsudot[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "uint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ],
      [
        "MOVPRFX",
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsudot[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svuint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ],
      [
        "MOVPRFX",
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svsudot_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint8_t op2",
      "svuint8_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUDOT"
      ],
      [
        "MOVPRFX",
        "SUDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svtbl2[_f16]",
    "arguments": [
      "svfloat16x2_t data",
      "svuint16_t indices"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "{Zdata0.H, Zdata1.H}"
      },
      "indices": {
        "register": "Zindices.H"
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    },
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      [
        "TRN1"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_f64]",
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      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
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      "value": "svfloat64_t"
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      "op1": {
        "register": "Zop1.D"
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      "op2": {
        "register": "Zop2.D"
      }
    },
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_s16]",
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      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
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      "op2": {
        "register": "Zop2.H"
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    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
    ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_s32]",
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      "svint32_t op1",
      "svint32_t op2"
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      "value": "svint32_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
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      "op1": {
        "register": "Zop1.D"
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      "op2": {
        "register": "Zop2.D"
      }
    },
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
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      "value": "svint8_t"
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      "op1": {
        "register": "Zop1.B"
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      "op2": {
        "register": "Zop2.B"
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    },
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
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      "value": "svuint16_t"
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      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
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      "value": "svuint32_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
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    "Architectures": [
      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1[_u8]",
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      "svuint8_t op1",
      "svuint8_t op2"
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      "value": "svuint8_t"
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      "op1": {
        "register": "Zop1.B"
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      "op2": {
        "register": "Zop2.B"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1_b16",
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      "svbool_t op1",
      "svbool_t op2"
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.H"
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      "op2": {
        "register": "Pop2.H"
      }
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1_b32",
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      "svbool_t op1",
      "svbool_t op2"
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.S"
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      "op2": {
        "register": "Pop2.S"
      }
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t op2"
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.D"
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      "op2": {
        "register": "Pop2.D"
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    "instructions": [
      [
        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t op2"
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      "value": "svbool_t"
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        "register": "Pop1.B"
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      "op2": {
        "register": "Pop2.B"
      }
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      "A64"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1q[_f16]",
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      "svfloat16_t op1",
      "svfloat16_t op2"
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      "value": "svfloat16_t"
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        "register": "Zop1.Q"
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      "op2": {
        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn1q[_f32]",
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      "svfloat32_t op2"
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      "value": "svfloat32_t"
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      "op1": {
        "register": "Zop1.Q"
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      "op2": {
        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat64_t op1",
      "svfloat64_t op2"
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      "value": "svfloat64_t"
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      "op1": {
        "register": "Zop1.Q"
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      "op2": {
        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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      "svint16_t op2"
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      "value": "svint16_t"
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        "register": "Zop1.Q"
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      "op2": {
        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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      "svint32_t op2"
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        "register": "Zop1.Q"
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      "op2": {
        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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      "svint64_t op2"
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        "register": "Zop1.Q"
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        "register": "Zop2.Q"
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        "TRN1"
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.Q"
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        "register": "Zop2.Q"
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        "TRN1"
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    "SIMD_ISA": "SVE",
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      "svuint16_t op2"
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        "register": "Zop1.Q"
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        "register": "Zop2.Q"
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        "TRN1"
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.Q"
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        "register": "Zop2.Q"
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        "TRN1"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop1.Q"
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        "register": "Zop2.Q"
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        "TRN1"
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    "SIMD_ISA": "SVE",
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      "svuint8_t op2"
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    "SIMD_ISA": "SVE",
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      "svfloat16_t op2"
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        "register": "Zop1.H"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop1.S"
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        "register": "Zop2.S"
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  {
    "SIMD_ISA": "SVE",
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      "svfloat64_t op2"
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        "register": "Zop1.D"
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        "TRN2"
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  {
    "SIMD_ISA": "SVE",
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      "svint16_t op2"
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        "register": "Zop1.H"
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        "register": "Zop2.H"
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        "TRN2"
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2[_s32]",
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      "svint32_t op2"
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        "register": "Zop1.S"
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.D"
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        "register": "Zop2.D"
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        "TRN2"
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  {
    "SIMD_ISA": "SVE",
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      "svint8_t op2"
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        "register": "Zop1.B"
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        "register": "Zop2.B"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "SVE",
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      "svuint16_t op2"
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        "register": "Zop1.H"
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        "register": "Zop2.H"
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      [
        "TRN2"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2[_u32]",
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      "svuint32_t op1",
      "svuint32_t op2"
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      "value": "svuint32_t"
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      "op1": {
        "register": "Zop1.S"
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        "register": "Zop2.S"
      }
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      [
        "TRN2"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2[_u64]",
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      "svuint64_t op1",
      "svuint64_t op2"
    ],
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      "value": "svuint64_t"
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      "op1": {
        "register": "Zop1.D"
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        "register": "Zop2.D"
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        "TRN2"
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    "SIMD_ISA": "SVE",
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      "svuint8_t op2"
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      "op1": {
        "register": "Zop1.B"
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        "register": "Zop2.B"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2_b16",
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      "svbool_t op2"
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      "value": "svbool_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.H"
      },
      "op2": {
        "register": "Pop2.H"
      }
    },
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    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2_b32",
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      "svbool_t op1",
      "svbool_t op2"
    ],
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.S"
      },
      "op2": {
        "register": "Pop2.S"
      }
    },
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    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2_b64",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.D"
      },
      "op2": {
        "register": "Pop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svtrn2_b8",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
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        "SUNPKHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpkhi[_u16]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpkhi[_u32]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpkhi[_u64]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_b]",
    "arguments": [
      "svbool_t op"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_s16]",
    "arguments": [
      "svint8_t op"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_s32]",
    "arguments": [
      "svint16_t op"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_s64]",
    "arguments": [
      "svint32_t op"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_u16]",
    "arguments": [
      "svuint8_t op"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_u32]",
    "arguments": [
      "svuint16_t op"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svunpklo[_u64]",
    "arguments": [
      "svuint32_t op"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Zop.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UUNPKLO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "uint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H[*]"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S[*]"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D[*]"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ],
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_n_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "uint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B[*]"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s16]_m",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s16]_x",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s16]_z",
    "arguments": [
      "svbool_t pg",
      "svint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      },
      "pg": {
        "register": "Pg.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s32]_m",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s32]_x",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s32]_z",
    "arguments": [
      "svbool_t pg",
      "svint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      },
      "pg": {
        "register": "Pg.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s64]_m",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s64]_x",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s64]_z",
    "arguments": [
      "svbool_t pg",
      "svint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      },
      "pg": {
        "register": "Pg.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s8]_m",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s8]_x",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ],
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svuqadd[_s8]_z",
    "arguments": [
      "svbool_t pg",
      "svint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "pg": {
        "register": "Pg.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOVPRFX",
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svusdot[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svuint8_t op2",
      "int8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B[*]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ],
      [
        "MOVPRFX",
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svusdot[_s32]",
    "arguments": [
      "svint32_t op1",
      "svuint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ],
      [
        "MOVPRFX",
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svusdot_lane[_s32]",
    "arguments": [
      "svint32_t op1",
      "svuint8_t op2",
      "svint8_t op3",
      "uint64_t imm_index"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm_index": {
        "minimum": 0,
        "maximum": 3
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ],
      [
        "MOVPRFX",
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svusmmla[_s32]",
    "arguments": [
      "svint32_t op1",
      "svuint8_t op2",
      "svint8_t op3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.B"
      },
      "op3": {
        "register": "Zop3.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USMMLA"
      ],
      [
        "MOVPRFX",
        "USMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1_b16",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.H"
      },
      "op2": {
        "register": "Pop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1_b32",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.S"
      },
      "op2": {
        "register": "Pop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1_b64",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.D"
      },
      "op2": {
        "register": "Pop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1_b8",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp1q[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.D"
      },
      "op2": {
        "register": "Zop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.B"
      },
      "op2": {
        "register": "Zop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svuzp2[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
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        "register": "Zop1.S"
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      "value": "svuint64_t"
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        "WHILEHS"
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  {
    "SIMD_ISA": "SVE2",
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        "register": "Xop1"
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    "SIMD_ISA": "SVE2",
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  {
    "SIMD_ISA": "SVE2",
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        "register": "Xop1"
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    "instructions": [
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        "WHILEGT"
      ]
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  {
    "SIMD_ISA": "SVE2",
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      "uint32_t op2"
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        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
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    "instructions": [
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        "WHILEHI"
      ]
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  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b16[_u64]",
    "arguments": [
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      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
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      "op2": {
        "register": "Xop2"
      }
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    ],
    "instructions": [
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        "WHILEHI"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b32[_s32]",
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      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "WHILEGT"
      ]
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  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b32[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILEGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b32[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b32[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b64[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b64[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILEGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b64[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b64[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b8[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b8[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b8[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilegt_b8[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b16[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b16[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b16[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b16[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b32[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b32[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b32[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b32[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b64[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b64[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b64[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b64[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b8[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b8[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELE"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b8[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilele_b8[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELS"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b16[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b16[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b16[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b16[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b32[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b32[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b32[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b32[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b64[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b64[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b64[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b64[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b8[_s32]",
    "arguments": [
      "int32_t op1",
      "int32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b8[_s64]",
    "arguments": [
      "int64_t op1",
      "int64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELT"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b8[_u32]",
    "arguments": [
      "uint32_t op1",
      "uint32_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Wop1"
      },
      "op2": {
        "register": "Wop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwhilelt_b8[_u64]",
    "arguments": [
      "uint64_t op1",
      "uint64_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILELO"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_f16]",
    "arguments": [
      "const float16_t *op1",
      "const float16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_f32]",
    "arguments": [
      "const float32_t *op1",
      "const float32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_f64]",
    "arguments": [
      "const float64_t *op1",
      "const float64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_s16]",
    "arguments": [
      "const int16_t *op1",
      "const int16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_s32]",
    "arguments": [
      "const int32_t *op1",
      "const int32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_s64]",
    "arguments": [
      "const int64_t *op1",
      "const int64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_s8]",
    "arguments": [
      "const int8_t *op1",
      "const int8_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_u16]",
    "arguments": [
      "const uint16_t *op1",
      "const uint16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_u32]",
    "arguments": [
      "const uint32_t *op1",
      "const uint32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_u64]",
    "arguments": [
      "const uint64_t *op1",
      "const uint64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilerw[_u8]",
    "arguments": [
      "const uint8_t *op1",
      "const uint8_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILERW"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_f16]",
    "arguments": [
      "const float16_t *op1",
      "const float16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_f32]",
    "arguments": [
      "const float32_t *op1",
      "const float32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_f64]",
    "arguments": [
      "const float64_t *op1",
      "const float64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_s16]",
    "arguments": [
      "const int16_t *op1",
      "const int16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_s32]",
    "arguments": [
      "const int32_t *op1",
      "const int32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_s64]",
    "arguments": [
      "const int64_t *op1",
      "const int64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_s8]",
    "arguments": [
      "const int8_t *op1",
      "const int8_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_u16]",
    "arguments": [
      "const uint16_t *op1",
      "const uint16_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_u32]",
    "arguments": [
      "const uint32_t *op1",
      "const uint32_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_u64]",
    "arguments": [
      "const uint64_t *op1",
      "const uint64_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svwhilewr[_u8]",
    "arguments": [
      "const uint8_t *op1",
      "const uint8_t *op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Xop1"
      },
      "op2": {
        "register": "Xop2"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WHILEWR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svwrffr",
    "arguments": [
      "svbool_t op"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "op": {
        "register": "Pop.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "WRFFR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 16
      },
      "op1": {
        "register": "Zop1.H|Ztied1.H"
      },
      "op2": {
        "register": "Zop2.H|Ztied2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 32
      },
      "op1": {
        "register": "Zop1.S|Ztied1.S"
      },
      "op2": {
        "register": "Zop2.S|Ztied2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 64
      },
      "op1": {
        "register": "Zop1.D|Ztied1.D"
      },
      "op2": {
        "register": "Zop2.D|Ztied2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE2",
    "name": "svxar[_n_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2",
      "uint64_t imm3"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "imm3": {
        "minimum": 1,
        "maximum": 8
      },
      "op1": {
        "register": "Zop1.B|Ztied1.B"
      },
      "op2": {
        "register": "Zop2.B|Ztied2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ],
      [
        "XAR"
      ],
      [
        "MOVPRFX",
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip1[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.H"
      },
      "op2": {
        "register": "Zop2.H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip1[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.S"
      },
      "op2": {
        "register": "Zop2.S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip1[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
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        "register": "Zop1.S"
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        "ZIP1"
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      "svint64_t op2"
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        "register": "Zop1.D"
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        "ZIP1"
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  {
    "SIMD_ISA": "SVE",
    "name": "svzip1[_s8]",
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      "svint8_t op2"
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        "register": "Zop1.B"
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        "register": "Zop2.B"
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        "ZIP1"
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    "SIMD_ISA": "SVE",
    "name": "svzip1[_u16]",
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      "svuint16_t op2"
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    "SIMD_ISA": "SVE",
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      "svuint32_t op2"
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        "register": "Zop1.S"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop1.D"
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        "register": "Zop2.D"
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        "ZIP1"
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  {
    "SIMD_ISA": "SVE",
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        "register": "Zop1.B"
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        "register": "Zop2.B"
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        "ZIP1"
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.H"
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      "op2": {
        "register": "Pop2.H"
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        "ZIP1"
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      "value": "svbool_t"
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      "op1": {
        "register": "Pop1.S"
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      "op2": {
        "register": "Pop2.S"
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        "ZIP1"
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        "register": "Pop1.D"
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      "op2": {
        "register": "Pop2.D"
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        "ZIP1"
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        "register": "Pop1.B"
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        "ZIP1"
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        "ZIP1"
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        "register": "Zop1.Q"
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        "ZIP1"
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        "ZIP1"
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.B"
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        "ZIP2"
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    "SIMD_ISA": "SVE",
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        "register": "Zop1.H"
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        "ZIP2"
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    "SIMD_ISA": "SVE",
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      "op1": {
        "register": "Zop1.S"
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        "register": "Zop2.S"
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        "ZIP2"
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  {
    "SIMD_ISA": "SVE",
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      "svuint64_t op2"
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        "register": "Zop1.D"
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        "ZIP2"
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  {
    "SIMD_ISA": "SVE",
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      "svuint8_t op2"
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        "register": "Zop1.B"
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        "register": "Zop2.B"
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        "ZIP2"
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t op2"
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      "op1": {
        "register": "Pop1.H"
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      "op2": {
        "register": "Pop2.H"
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    ],
    "instructions": [
      [
        "ZIP2"
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  {
    "SIMD_ISA": "SVE",
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      "svbool_t op2"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.S"
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      "op2": {
        "register": "Pop2.S"
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    ],
    "instructions": [
      [
        "ZIP2"
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  },
  {
    "SIMD_ISA": "SVE",
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      "svbool_t op2"
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    "return_type": {
      "value": "svbool_t"
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    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.D"
      },
      "op2": {
        "register": "Pop2.D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2_b8",
    "arguments": [
      "svbool_t op1",
      "svbool_t op2"
    ],
    "return_type": {
      "value": "svbool_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Pop1.B"
      },
      "op2": {
        "register": "Pop2.B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_f16]",
    "arguments": [
      "svfloat16_t op1",
      "svfloat16_t op2"
    ],
    "return_type": {
      "value": "svfloat16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_f32]",
    "arguments": [
      "svfloat32_t op1",
      "svfloat32_t op2"
    ],
    "return_type": {
      "value": "svfloat32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_f64]",
    "arguments": [
      "svfloat64_t op1",
      "svfloat64_t op2"
    ],
    "return_type": {
      "value": "svfloat64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_s16]",
    "arguments": [
      "svint16_t op1",
      "svint16_t op2"
    ],
    "return_type": {
      "value": "svint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_s32]",
    "arguments": [
      "svint32_t op1",
      "svint32_t op2"
    ],
    "return_type": {
      "value": "svint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_s64]",
    "arguments": [
      "svint64_t op1",
      "svint64_t op2"
    ],
    "return_type": {
      "value": "svint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_s8]",
    "arguments": [
      "svint8_t op1",
      "svint8_t op2"
    ],
    "return_type": {
      "value": "svint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_u16]",
    "arguments": [
      "svuint16_t op1",
      "svuint16_t op2"
    ],
    "return_type": {
      "value": "svuint16_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_u32]",
    "arguments": [
      "svuint32_t op1",
      "svuint32_t op2"
    ],
    "return_type": {
      "value": "svuint32_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_u64]",
    "arguments": [
      "svuint64_t op1",
      "svuint64_t op2"
    ],
    "return_type": {
      "value": "svuint64_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "SVE",
    "name": "svzip2q[_u8]",
    "arguments": [
      "svuint8_t op1",
      "svuint8_t op2"
    ],
    "return_type": {
      "value": "svuint8_t"
    },
    "Arguments_Preparation": {
      "op1": {
        "register": "Zop1.Q"
      },
      "op2": {
        "register": "Zop2.Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabds_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p128",
    "arguments": [
      "poly128_t a",
      "poly128_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesdq_u8",
    "arguments": [
      "uint8x16_t data",
      "uint8x16_t key"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vd.16B"
      },
      "key": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaeseq_u8",
    "arguments": [
      "uint8x16_t data",
      "uint8x16_t key"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vd.16B"
      },
      "key": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesimcq_u8",
    "arguments": [
      "uint8x16_t data"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESIMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesmcq_u8",
    "arguments": [
      "uint8x16_t data"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamax_f16",
    "arguments": [
      "float16x4_t vn",
      "float16x4_t vm"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4H"
      },
      "vn": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamax_f32",
    "arguments": [
      "float32x2_t vn",
      "float32x2_t vm"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2S"
      },
      "vn": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamaxq_f16",
    "arguments": [
      "float16x8_t vn",
      "float16x8_t vm"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.8H"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamaxq_f32",
    "arguments": [
      "float32x4_t vn",
      "float32x4_t vm"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4S"
      },
      "vn": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamaxq_f64",
    "arguments": [
      "float64x2_t vn",
      "float64x2_t vm"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2D"
      },
      "vn": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamin_f16",
    "arguments": [
      "float16x4_t vn",
      "float16x4_t vm"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4H"
      },
      "vn": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamin_f32",
    "arguments": [
      "float32x2_t vn",
      "float32x2_t vm"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2S"
      },
      "vn": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaminq_f16",
    "arguments": [
      "float16x8_t vn",
      "float16x8_t vm"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.8H"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaminq_f32",
    "arguments": [
      "float32x4_t vn",
      "float32x4_t vm"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4S"
      },
      "vn": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaminq_f64",
    "arguments": [
      "float64x2_t vn",
      "float64x2_t vm"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2D"
      },
      "vn": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "int64x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "uint64x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbcaxq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "c": {
        "register": "Va.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BCAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbic_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbicq_u8",
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      "uint8x16_t a",
      "uint8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BIC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_f16",
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      "uint16x4_t a",
      "float16x4_t b",
      "float16x4_t c"
    ],
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      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_f32",
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      "uint32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
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      "value": "float32x2_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_f64",
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      "uint64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
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      "value": "float64x1_t"
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "poly16x4_t b",
      "poly16x4_t c"
    ],
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      "value": "poly16x4_t"
    },
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        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_p64",
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      "poly64x1_t a",
      "poly64x1_t b",
      "poly64x1_t c"
    ],
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      "value": "poly64x1_t"
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "poly8x8_t b",
      "poly8x8_t c"
    ],
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      "value": "poly8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
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      "value": "int16x4_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_s32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
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      "value": "int32x2_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x1_t a",
      "int64x1_t b",
      "int64x1_t c"
    ],
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      "value": "int64x1_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
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      "value": "int8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
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      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "uint64x1_t c"
    ],
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f16",
    "arguments": [
      "uint16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f32",
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      "uint32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f64",
    "arguments": [
      "uint64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p16",
    "arguments": [
      "uint16x8_t a",
      "poly16x8_t b",
      "poly16x8_t c"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b",
      "poly64x2_t c"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p8",
    "arguments": [
      "uint8x16_t a",
      "poly8x16_t b",
      "poly8x16_t c"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
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      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b",
      "int64x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "uint64x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot270_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot270_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot90_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot90_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaged_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcages_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
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      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
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      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaled_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcales_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqs_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_p64",
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      "poly64x1_t a"
    ],
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
      }
    },
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      "A32",
      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "poly8x8_t a"
    ],
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
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    },
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      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_s16",
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      "int16x4_t a"
    ],
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a"
    ],
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      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
      }
    },
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      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a"
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
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      "A64"
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqz_s8",
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      "int8x8_t a"
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
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      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a"
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      "value": "uint16x4_t"
    },
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        "register": "Vn.4H"
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      "A64"
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a"
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      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint64x1_t a"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint8x8_t a"
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64_t a"
    ],
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
      }
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        "FCMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vceqzd_s64",
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      "int64_t a"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
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        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vceqzd_u64",
    "arguments": [
      "uint64_t a"
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      "value": "uint64_t"
    },
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        "register": "Dn"
      }
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      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzh_f16",
    "arguments": [
      "float16_t a"
    ],
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Hn"
      }
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    ],
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      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f16",
    "arguments": [
      "float16x8_t a"
    ],
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
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      "A32",
      "A64"
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      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f32",
    "arguments": [
      "float32x4_t a"
    ],
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "A64"
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        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f64",
    "arguments": [
      "float64x2_t a"
    ],
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "A64"
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      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "poly64x2_t a"
    ],
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "A32",
      "A64"
    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "poly8x16_t a"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
      }
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x8_t a"
    ],
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      "value": "uint16x8_t"
    },
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        "register": "Vn.8H"
      }
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    ],
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a"
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
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        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s64",
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      "int64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
      }
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s8",
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      "int8x16_t a"
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    },
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      "a": {
        "register": "Vn.16B"
      }
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      "A64"
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_u16",
    "arguments": [
      "uint16x8_t a"
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
    },
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      "A64"
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x4_t a"
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x2_t a"
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      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
      }
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t a"
    ],
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    },
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      "a": {
        "register": "Vn.16B"
      }
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      "A64"
    ],
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        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzs_f32",
    "arguments": [
      "float32_t a"
    ],
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      "value": "uint32_t"
    },
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      "a": {
        "register": "Sn"
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    },
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        "FCMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
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      "value": "uint16x4_t"
    },
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
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      "A64"
    ],
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
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      "value": "uint32x2_t"
    },
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
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    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcges_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezd_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzd_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtzs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcle_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcled_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcled_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcled_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
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      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
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      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
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      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_s64",
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      "int64x2_t a",
      "int64x2_t b"
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      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_s8",
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      "int8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u32",
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      "uint32x4_t a",
      "uint32x4_t b"
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      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u8",
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      "uint8x16_t a",
      "uint8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcles_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
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      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f16",
    "arguments": [
      "float16x4_t a"
    ],
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f64",
    "arguments": [
      "float64x1_t a"
    ],
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s16",
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      "int16x4_t a"
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s32",
    "arguments": [
      "int32x2_t a"
    ],
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      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s64",
    "arguments": [
      "int64x1_t a"
    ],
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      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s8",
    "arguments": [
      "int8x8_t a"
    ],
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezd_f64",
    "arguments": [
      "float64_t a"
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    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezd_s64",
    "arguments": [
      "int64_t a"
    ],
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      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezh_f16",
    "arguments": [
      "float16_t a"
    ],
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      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f32",
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      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
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      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
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      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
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      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s32",
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      "int32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
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      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
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      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "CMHI"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
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      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "FCMGT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
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      "A32",
      "A64"
    ],
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      [
        "FCMGT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a",
      "float32x4_t b"
    ],
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      "value": "uint32x4_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
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      "A32",
      "A64"
    ],
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        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
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    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_s32",
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      "int32x4_t a",
      "int32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
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      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
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    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
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      "A32",
      "A64"
    ],
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      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
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      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_f16",
    "arguments": [
      "float16x4_t a"
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_s64",
    "arguments": [
      "int64x1_t a"
    ],
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzd_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_s64",
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      "int64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "A64"
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        "CMLT"
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_s8",
    "arguments": [
      "int8x16_t a"
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "A64"
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        "CMLT"
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    "SIMD_ISA": "Neon",
    "name": "vcltzs_f32",
    "arguments": [
      "float32_t a"
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      "value": "uint32_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
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      "A64"
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        "FCMLT"
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    "name": "vclz_s16",
    "arguments": [
      "int16x4_t a"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    "SIMD_ISA": "Neon",
    "name": "vclz_s32",
    "arguments": [
      "int32x2_t a"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "A32",
      "A64"
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        "CLZ"
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    "name": "vclz_s8",
    "arguments": [
      "int8x8_t a"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    "SIMD_ISA": "Neon",
    "name": "vclz_u16",
    "arguments": [
      "uint16x4_t a"
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    "return_type": {
      "value": "uint16x4_t"
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        "register": "Vn.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    "SIMD_ISA": "Neon",
    "name": "vclz_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "v7",
      "A32",
      "A64"
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      [
        "CLZ"
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    "SIMD_ISA": "Neon",
    "name": "vclz_u8",
    "arguments": [
      "uint8x8_t a"
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    "return_type": {
      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    ]
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    "SIMD_ISA": "Neon",
    "name": "vclzq_s16",
    "arguments": [
      "int16x8_t a"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    ]
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    "SIMD_ISA": "Neon",
    "name": "vclzq_s32",
    "arguments": [
      "int32x4_t a"
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    "return_type": {
      "value": "int32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "A32",
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      [
        "CLZ"
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      "int8x16_t a"
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      "value": "int8x16_t"
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      "a": {
        "register": "Vn.16B"
      }
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    "name": "vclzq_u16",
    "arguments": [
      "uint16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
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    ]
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    "SIMD_ISA": "Neon",
    "name": "vclzq_u32",
    "arguments": [
      "uint32x4_t a"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "v7",
      "A32",
      "A64"
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      [
        "CLZ"
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    "SIMD_ISA": "Neon",
    "name": "vclzq_u8",
    "arguments": [
      "uint8x16_t a"
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
      }
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    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
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  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
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      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
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      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b"
    ],
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      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_lane_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
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        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_lane_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b",
      "const int lane"
    ],
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      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
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      [
        "FCMLA"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_laneq_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
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      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_laneq_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x4_t b",
      "const int lane"
    ],
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      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        ""
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_lane_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_lane_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_laneq_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot180_laneq_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        ""
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_lane_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_lane_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_laneq_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot270_laneq_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        ""
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_lane_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_lane_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_laneq_f16",
    "arguments": [
      "float16x4_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmla_rot90_laneq_f32",
    "arguments": [
      "float32x2_t r",
      "float32x2_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        ""
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_lane_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_lane_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_laneq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_laneq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_lane_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_lane_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_laneq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_laneq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_lane_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_lane_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_laneq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_laneq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_lane_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_lane_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_laneq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_laneq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f16",
    "arguments": [
      "float16x4_t low",
      "float16x4_t high"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f32",
    "arguments": [
      "float32x2_t low",
      "float32x2_t high"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f64",
    "arguments": [
      "float64x1_t low",
      "float64x1_t high"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p16",
    "arguments": [
      "poly16x4_t low",
      "poly16x4_t high"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p64",
    "arguments": [
      "poly64x1_t low",
      "poly64x1_t high"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p8",
    "arguments": [
      "poly8x8_t low",
      "poly8x8_t high"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s16",
    "arguments": [
      "int16x4_t low",
      "int16x4_t high"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s32",
    "arguments": [
      "int32x2_t low",
      "int32x2_t high"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s64",
    "arguments": [
      "int64x1_t low",
      "int64x1_t high"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s8",
    "arguments": [
      "int8x8_t low",
      "int8x8_t high"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u16",
    "arguments": [
      "uint16x4_t low",
      "uint16x4_t high"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u32",
    "arguments": [
      "uint32x2_t low",
      "uint32x2_t high"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u64",
    "arguments": [
      "uint64x1_t low",
      "uint64x1_t high"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u8",
    "arguments": [
      "uint8x8_t low",
      "uint8x8_t high"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_f32",
    "arguments": [
      "float32x2_t a",
      "const int lane1",
      "float32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_f64",
    "arguments": [
      "float64x1_t a",
      "const int lane1",
      "float64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p16",
    "arguments": [
      "poly16x4_t a",
      "const int lane1",
      "poly16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p64",
    "arguments": [
      "poly64x1_t a",
      "const int lane1",
      "poly64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p8",
    "arguments": [
      "poly8x8_t a",
      "const int lane1",
      "poly8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s16",
    "arguments": [
      "int16x4_t a",
      "const int lane1",
      "int16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s32",
    "arguments": [
      "int32x2_t a",
      "const int lane1",
      "int32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s64",
    "arguments": [
      "int64x1_t a",
      "const int lane1",
      "int64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s8",
    "arguments": [
      "int8x8_t a",
      "const int lane1",
      "int8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "const int lane1",
      "uint16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "const int lane1",
      "uint32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
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      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u64",
    "arguments": [
      "uint64x1_t a",
      "const int lane1",
      "uint64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
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        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u8",
    "arguments": [
      "uint8x8_t a",
      "const int lane1",
      "uint8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
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      "b": {
        "register": "Vn.8B"
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        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "const int lane1",
      "float32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4S"
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "const int lane1",
      "float64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
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      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p16",
    "arguments": [
      "poly16x4_t a",
      "const int lane1",
      "poly16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
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      "b": {
        "register": "Vn.8H"
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        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
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    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p64",
    "arguments": [
      "poly64x1_t a",
      "const int lane1",
      "poly64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
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      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
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      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p8",
    "arguments": [
      "poly8x8_t a",
      "const int lane1",
      "poly8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "const int lane1",
      "int16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
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        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "const int lane1",
      "int32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
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      "b": {
        "register": "Vn.4S"
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      "lane1": {
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s64",
    "arguments": [
      "int64x1_t a",
      "const int lane1",
      "int64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s8",
    "arguments": [
      "int8x8_t a",
      "const int lane1",
      "int8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "const int lane1",
      "uint16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
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        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "const int lane1",
      "uint32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
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      "b": {
        "register": "Vn.4S"
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u64",
    "arguments": [
      "uint64x1_t a",
      "const int lane1",
      "uint64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u8",
    "arguments": [
      "uint8x8_t a",
      "const int lane1",
      "uint8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "const int lane1",
      "float32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
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        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "const int lane1",
      "float64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p16",
    "arguments": [
      "poly16x8_t a",
      "const int lane1",
      "poly16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p64",
    "arguments": [
      "poly64x2_t a",
      "const int lane1",
      "poly64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p8",
    "arguments": [
      "poly8x16_t a",
      "const int lane1",
      "poly8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "const int lane1",
      "int16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "const int lane1",
      "int32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s64",
    "arguments": [
      "int64x2_t a",
      "const int lane1",
      "int64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s8",
    "arguments": [
      "int8x16_t a",
      "const int lane1",
      "int8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "const int lane1",
      "uint16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "const int lane1",
      "uint32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u64",
    "arguments": [
      "uint64x2_t a",
      "const int lane1",
      "uint64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u8",
    "arguments": [
      "uint8x16_t a",
      "const int lane1",
      "uint8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "const int lane1",
      "float32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "const int lane1",
      "float64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p16",
    "arguments": [
      "poly16x8_t a",
      "const int lane1",
      "poly16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p64",
    "arguments": [
      "poly64x2_t a",
      "const int lane1",
      "poly64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p8",
    "arguments": [
      "poly8x16_t a",
      "const int lane1",
      "poly8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "const int lane1",
      "int16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "const int lane1",
      "int32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s64",
    "arguments": [
      "int64x2_t a",
      "const int lane1",
      "int64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s8",
    "arguments": [
      "int8x16_t a",
      "const int lane1",
      "int8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "const int lane1",
      "uint16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "const int lane1",
      "uint32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u64",
    "arguments": [
      "uint64x2_t a",
      "const int lane1",
      "uint64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u8",
    "arguments": [
      "uint8x16_t a",
      "const int lane1",
      "uint8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f32",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p8",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s32",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s8",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u32",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u8",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f32_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f32_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f64_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_high_f16_f32",
    "arguments": [
      "float16x4_t r",
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_high_f32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
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      [
        "FCVTL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32x2_t r",
      "float64x2_t a"
    ],
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn.2D"
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        "register": "Vd.2S"
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      "A64"
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      [
        "FCVTN2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "float64x2_t"
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        "register": "Vn.4S"
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        "FCVTL2"
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  },
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      "const int n"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
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      "A64"
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        "SCVTF"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
    ],
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      "value": "float16x4_t"
    },
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
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      "A64"
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      [
        "UCVTF"
      ]
    ]
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        "register": "Vn.2S"
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      "A64"
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        "SCVTF"
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        "register": "Vn.2S"
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      "A64"
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        "UCVTF"
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    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "SCVTF"
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        "register": "Dn"
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        "UCVTF"
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        "register": "Vn.4H"
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        "FCVTZS"
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        "FCVTZS"
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        "register": "Dn"
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        "FCVTZS"
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        "FCVTZU"
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        "FCVTZU"
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        "register": "Dn"
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        "FCVTZU"
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        "FCVTZS"
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        "register": "Vn.2S"
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        "FCVTZS"
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      "A64"
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        "FCVTZS"
      ]
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        "register": "Vn.2S"
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        "FCVTZU"
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        "register": "Dn"
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        "FCVTZU"
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        "register": "Vn.4H"
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        "FCVTAS"
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        "register": "Vn.2S"
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        "FCVTAS"
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        "FCVTAS"
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        "register": "Vn.4H"
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      "A64"
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        "FCVTAU"
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      "A64"
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        "register": "Dn"
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        "FCVTAU"
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        "register": "Dn"
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        "register": "Dn"
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        "FCVTAS"
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        "register": "Dn"
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        "FCVTAU"
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        "register": "Dn"
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        "FCVTAU"
      ]
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      "float16_t a"
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      "value": "int16_t"
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        "register": "Hn"
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        "register": "Hn"
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        "FCVTAS"
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        "register": "Hn"
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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        "register": "Hn"
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        "FCVTAU"
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    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "uint32_t"
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        "register": "Hn"
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        "FCVTAU"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint64_t"
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        "register": "Hn"
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      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a"
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        "register": "Vn.8H"
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      "A64"
    ],
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        "FCVTAS"
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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      "A64"
    ],
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        "FCVTAS"
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  {
    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.2D"
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        "FCVTAS"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a"
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
      }
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      "A64"
    ],
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        "FCVTAU"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "uint32x4_t"
    },
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        "register": "Vn.4S"
      }
    },
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      "A64"
    ],
    "instructions": [
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        "FCVTAU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtaq_u64_f64",
    "arguments": [
      "float64x2_t a"
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      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FCVTAU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtas_s32_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "FCVTAS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_u32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_u64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_f32_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_f32_u32",
    "arguments": [
      "uint32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_f32_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_f32_u32",
    "arguments": [
      "uint32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_s32_f32",
    "arguments": [
      "float32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_u32_f32",
    "arguments": [
      "float32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_s32_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_s64_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_u32_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_u64_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtx_f32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtx_high_f32_f64",
    "arguments": [
      "float32x2_t r",
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtxd_f32_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_lane_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_laneq_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_laneq_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_lane_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_lane_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_laneq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_laneq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdup_lane_f16",
    "arguments": [
      "float16x4_t vec",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdup_lane_f32",
    "arguments": [
      "float32x2_t vec",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "vec": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdup_lane_f64",
    "arguments": [
      "float64x1_t vec",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "vec": {
        "register": "Vn.1D"
      }
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      "vec": {
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        "DUP"
      ]
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "DUP"
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        "DUP"
      ]
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        "DUP"
      ]
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  {
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      "value": "uint16x8_t"
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        "DUP"
      ]
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  {
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      [
        "DUP"
      ]
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  {
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        "register": "Vn.2D"
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      [
        "DUP"
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  {
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      [
        "DUP"
      ]
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    "SIMD_ISA": "Neon",
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      "float16_t value"
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      "value": {
        "register": "rn"
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      "A64"
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        "DUP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32_t value"
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      "value": {
        "register": "rn"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
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    "SIMD_ISA": "Neon",
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      "float64_t value"
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      "value": {
        "register": "rn"
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      [
        "DUP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly16_t value"
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      "value": "poly16x8_t"
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      "value": {
        "register": "rn"
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        "DUP"
      ]
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    "SIMD_ISA": "Neon",
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      "poly64_t value"
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      "value": "poly64x2_t"
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      "value": {
        "register": "rn"
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      "A64"
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      [
        "DUP"
      ]
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  {
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      "poly8_t value"
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      "value": {
        "register": "rn"
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "int16_t value"
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      "value": {
        "register": "rn"
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      "A64"
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        "DUP"
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      "int32_t value"
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      "value": "int32x4_t"
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      "value": {
        "register": "rn"
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      "A64"
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "int64_t value"
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      "value": {
        "register": "rn"
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      "A64"
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        "DUP"
      ]
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    "SIMD_ISA": "Neon",
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      "int8_t value"
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      "value": "int8x16_t"
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      "value": {
        "register": "rn"
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      "A32",
      "A64"
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "uint16_t value"
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      "value": "uint16x8_t"
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      "value": {
        "register": "rn"
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      "A64"
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      [
        "DUP"
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    "SIMD_ISA": "Neon",
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      "uint32_t value"
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      "value": "uint32x4_t"
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      "value": {
        "register": "rn"
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      "A64"
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      [
        "DUP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint64_t value"
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      "value": "uint64x2_t"
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      "value": {
        "register": "rn"
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      "A64"
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "uint8_t value"
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      "value": {
        "register": "rn"
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      "A64"
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      [
        "DUP"
      ]
    ]
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    "SIMD_ISA": "Neon",
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      "const int lane"
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      "value": "float32_t"
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        "minimum": 0,
        "maximum": 1
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      "vec": {
        "register": "Vn.2S"
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      [
        "DUP"
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      "value": "int32_t"
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        "minimum": 0,
        "maximum": 1
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        "register": "Vn.2S"
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      [
        "DUP"
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    "SIMD_ISA": "Neon",
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      "value": "uint32_t"
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        "DUP"
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  {
    "SIMD_ISA": "Neon",
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      "value": "float32_t"
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        "maximum": 3
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        "DUP"
      ]
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      "value": "int32_t"
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        "maximum": 3
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "value": "uint32_t"
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        "minimum": 0,
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        "DUP"
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        "register": "Vn.16B"
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        "register": "Vn.16B"
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        "register": "Vn.16B"
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      "value": "uint32x4_t"
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        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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        "register": "Va.16B"
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        "EOR3"
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    "SIMD_ISA": "Neon",
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      "uint64x2_t b",
      "uint64x2_t c"
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      "value": "uint64x2_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "register": "Va.16B"
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        "EOR3"
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    "SIMD_ISA": "Neon",
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      "uint8x16_t b",
      "uint8x16_t c"
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      "value": "uint8x16_t"
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        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
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        "register": "Va.16B"
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        "EOR3"
      ]
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    "SIMD_ISA": "Neon",
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      "int16x4_t b"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "EOR"
      ]
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    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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      "value": "int32x2_t"
    },
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
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      "A32",
      "A64"
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    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "veor_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "veor_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "veor_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
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        "EXT"
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      [
        "EXT"
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  {
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      [
        "EXT"
      ]
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    "instructions": [
      [
        "EXT"
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "instructions": [
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        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
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        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      [
        "EXT"
      ]
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    "instructions": [
      [
        "EXT"
      ]
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    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      [
        "EXT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t c"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "c": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmad_lane_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmad_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16_t c"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Ha"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_lane_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "c": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmas_lane_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmas_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vd.2H"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_lane_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_lane_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_laneq_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_laneq_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vd.2H"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vd.4H"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_lane_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_lane_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_laneq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_laneq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vd.4H"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vd.2H"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_lane_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_lane_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_laneq_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_laneq_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2H"
      },
      "b": {
        "register": "Vd.2H"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vd.4H"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_lane_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_lane_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_laneq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_laneq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vm.H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vd.4H"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t c"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "c": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsd_lane_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsd_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16_t c"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Ha"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "c": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmss_lane_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmss_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f64",
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      "float64x2_t a"
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      "value": "float64x1_t"
    },
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      "a": {
        "register": "Vn.2D"
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      "A64"
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      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_p16",
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      "poly16x8_t a"
    ],
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      "value": "poly16x4_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_p64",
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      "poly64x2_t a"
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      "value": "poly64x1_t"
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        "register": "Vn.2D"
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      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "poly8x16_t a"
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      "value": "poly8x8_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a"
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      "value": "int16x4_t"
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        "register": "Vn.8H"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_s32",
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      "int32x4_t a"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.4S"
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_s64",
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      "int64x2_t a"
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      "value": "int64x1_t"
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      "a": {
        "register": "Vn.2D"
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a"
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      "value": "int8x8_t"
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        "register": "Vn.16B"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_u16",
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      "uint16x8_t a"
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      "value": "uint16x4_t"
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        "register": "Vn.8H"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a"
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      "value": "uint32x2_t"
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        "register": "Vn.4S"
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_u64",
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      "uint64x2_t a"
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        "register": "Vn.2D"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t a"
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      "value": "uint8x8_t"
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        "register": "Vn.16B"
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x4_t v",
      "const int lane"
    ],
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      "value": "float16_t"
    },
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        "minimum": 0,
        "maximum": 3
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        "register": "Vn.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x2_t v",
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      "value": "float32_t"
    },
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        "minimum": 0,
        "maximum": 1
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        "register": "Vn.2S"
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      "A32",
      "A64"
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    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "value": "float64_t"
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        "minimum": 0,
        "maximum": 0
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        "register": "Vn.1D"
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      [
        "DUP"
      ]
    ]
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  {
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      "value": "poly16_t"
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        "minimum": 0,
        "maximum": 3
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        "register": "Vn.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UMOV"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "poly64_t"
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        "minimum": 0,
        "maximum": 0
      },
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        "register": "Vn.1D"
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      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "poly8_t"
    },
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        "minimum": 0,
        "maximum": 7
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      "v": {
        "register": "Vn.8B"
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      "A32",
      "A64"
    ],
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        "UMOV"
      ]
    ]
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  {
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      "value": "int16_t"
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        "minimum": 0,
        "maximum": 3
      },
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        "register": "Vn.4H"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "const int lane"
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      "value": "int32_t"
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        "minimum": 0,
        "maximum": 1
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      "v": {
        "register": "Vn.2S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_s64",
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      "const int lane"
    ],
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      "value": "int64_t"
    },
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        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vn.1D"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_s8",
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      "int8x8_t v",
      "const int lane"
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      "value": "int8_t"
    },
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        "minimum": 0,
        "maximum": 7
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      "v": {
        "register": "Vn.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_u16",
    "arguments": [
      "uint16x4_t v",
      "const int lane"
    ],
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      "value": "uint16_t"
    },
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        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4H"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_u32",
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      "uint32x2_t v",
      "const int lane"
    ],
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      "value": "uint32_t"
    },
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        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_u64",
    "arguments": [
      "uint64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64_t"
    },
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        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vn.1D"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_lane_u8",
    "arguments": [
      "uint8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8_t"
    },
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        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_f64",
    "arguments": [
      "float64x2_t a"
    ],
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      "value": "float64x1_t"
    },
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      "a": {
        "register": "Vn.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
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      "a": {
        "register": "Vn.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f16",
    "arguments": [
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f32",
    "arguments": [
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f64",
    "arguments": [
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p16",
    "arguments": [
      "poly16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p64",
    "arguments": [
      "poly64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p8",
    "arguments": [
      "poly8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s16",
    "arguments": [
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s32",
    "arguments": [
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s64",
    "arguments": [
      "int64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s8",
    "arguments": [
      "int8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u16",
    "arguments": [
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u32",
    "arguments": [
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u64",
    "arguments": [
      "uint64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u8",
    "arguments": [
      "uint8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x2",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x3",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x4",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x2",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x3",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x4",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x2",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x3",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x4",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x2",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x3",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x4",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x2",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x3",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x4",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x2",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x3",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x4",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x2",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x3",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x4",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x2",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x3",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x4",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x2",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x3",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x4",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x2",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x3",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x4",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x2",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x3",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x4",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x2",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x3",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x4",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x2",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x3",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x4",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x2",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x3",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x4",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x2",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x3",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x4",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x2",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x3",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x4",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x2",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x3",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x4",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x2",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x3",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x4",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x2",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x3",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x4",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x2",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x3",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x4",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x2",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x3",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x4",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x2",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x3",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x4",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x2",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x3",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x4",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x2",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x3",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x4",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x2",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x3",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x4",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x2",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x3",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x4",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x2",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x3",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x4",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x2",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x3",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x4",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
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      "value": "float16x4x2_t"
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        "register": "Xn"
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        "register": "Xn"
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        "register": "Xn"
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        "register": "Xn"
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      "A64"
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        "LD2"
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    "SIMD_ISA": "Neon",
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      "value": "int64x1x2_t"
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      "ptr": {
        "register": "Xn"
      }
    },
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      "A64"
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    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      },
      "src.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      },
      "src.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      },
      "src.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      },
      "src.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      },
      "src.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      },
      "src.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      },
      "src.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      },
      "src.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      },
      "src.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      },
      "src.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4H"
      },
      "src.val[1]": {
        "register": "Vt2.4H"
      },
      "src.val[2]": {
        "register": "Vt3.4H"
      },
      "src.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2S"
      },
      "src.val[1]": {
        "register": "Vt2.2S"
      },
      "src.val[2]": {
        "register": "Vt3.2S"
      },
      "src.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.1D"
      },
      "src.val[1]": {
        "register": "Vt2.1D"
      },
      "src.val[2]": {
        "register": "Vt3.1D"
      },
      "src.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8B"
      },
      "src.val[1]": {
        "register": "Vt2.8B"
      },
      "src.val[2]": {
        "register": "Vt3.8B"
      },
      "src.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      },
      "src.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      },
      "src.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      },
      "src.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      },
      "src.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      },
      "src.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      },
      "src.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      },
      "src.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      },
      "src.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      },
      "src.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      },
      "src.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.8H"
      },
      "src.val[1]": {
        "register": "Vt2.8H"
      },
      "src.val[2]": {
        "register": "Vt3.8H"
      },
      "src.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.4S"
      },
      "src.val[1]": {
        "register": "Vt2.4S"
      },
      "src.val[2]": {
        "register": "Vt3.4S"
      },
      "src.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.2D"
      },
      "src.val[1]": {
        "register": "Vt2.2D"
      },
      "src.val[2]": {
        "register": "Vt3.2D"
      },
      "src.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src.val[0]": {
        "register": "Vt.16B"
      },
      "src.val[1]": {
        "register": "Vt2.16B"
      },
      "src.val[2]": {
        "register": "Vt3.16B"
      },
      "src.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldap1q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LDAP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldrq_p128",
    "arguments": [
      "poly128_t const * ptr"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LDR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_f16",
    "arguments": [
      "float16x4_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_p16",
    "arguments": [
      "poly16x4_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_p8",
    "arguments": [
      "poly8x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_s16",
    "arguments": [
      "int16x4_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_s8",
    "arguments": [
      "int8x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_u16",
    "arguments": [
      "uint16x4_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_u8",
    "arguments": [
      "uint8x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_f16",
    "arguments": [
      "float16x4_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_p16",
    "arguments": [
      "poly16x4_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_p8",
    "arguments": [
      "poly8x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_s16",
    "arguments": [
      "int16x4_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_s8",
    "arguments": [
      "int8x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_u16",
    "arguments": [
      "uint16x4_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_laneq_u8",
    "arguments": [
      "uint8x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_f16",
    "arguments": [
      "float16x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_p16",
    "arguments": [
      "poly16x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_p8",
    "arguments": [
      "poly8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_s16",
    "arguments": [
      "int16x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_s8",
    "arguments": [
      "int8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_u16",
    "arguments": [
      "uint16x8_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_u8",
    "arguments": [
      "uint8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_laneq_f16",
    "arguments": [
      "float16x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_laneq_p16",
    "arguments": [
      "poly16x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_laneq_p8",
    "arguments": [
      "poly8x16_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_laneq_s16",
    "arguments": [
      "int16x8_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "index": {
        "minimum": 0,
        "maximum": 7
      },
      "vm": {
        "register": "Vm"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t vm",
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      "value": "int8x16_t"
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        "minimum": 0,
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        "register": "Vm"
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        "register": "Vn.16B"
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        "LUTI2"
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      "uint8x16_t vm",
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      "value": "uint16x8_t"
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        "minimum": 0,
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        "LUTI2"
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        "minimum": 0,
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        "register": "Vm"
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        "LUTI2"
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      "uint8x8_t vm",
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    ],
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      "value": "float16x8_t"
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        "minimum": 0,
        "maximum": 1
      },
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        "LUTI4"
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        "LUTI4"
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        "LUTI4"
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        "LUTI4"
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        "maximum": 0
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        "LUTI4"
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        "LUTI4"
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      "uint8x8_t vm",
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      "value": "uint8x16_t"
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        "LUTI4"
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    "SIMD_ISA": "Neon",
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      "uint8x16_t vm",
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    ],
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      "value": "float16x8_t"
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        "maximum": 3
      },
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        "LUTI4"
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      "uint8x16_t vm",
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    ],
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      "value": "poly16x8_t"
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      },
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      "vn.val[1]": {
        "register": "Vn2.8H"
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      "uint8x16_t vm",
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      "value": "poly8x16_t"
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        "maximum": 1
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        "register": "Vn.16B"
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        "LUTI4"
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      "value": "int16x8_t"
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        "maximum": 3
      },
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        "register": "Vn2.8H"
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        "maximum": 1
      },
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        "register": "Vn.16B"
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        "LUTI4"
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      "uint8x16_t vm",
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    ],
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      "value": "uint16x8_t"
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        "maximum": 3
      },
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        "register": "Vm"
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      "vn.val[1]": {
        "register": "Vn2.8H"
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        "LUTI4"
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      "uint8x16_t vm",
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      "value": "uint8x16_t"
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        "minimum": 0,
        "maximum": 1
      },
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        "register": "Vm"
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        "register": "Vn.16B"
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        "LUTI4"
      ]
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      "float16x4_t b"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
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        "FMAX"
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      "float32x2_t b"
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      "b": {
        "register": "Vm.2S"
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      "A64"
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      "value": "float64x1_t"
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        "register": "Dn"
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        "register": "Dm"
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        "FMAX"
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        "register": "Vn.4H"
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      "A64"
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      "int32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A64"
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      "int8x8_t b"
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      "value": "int8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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        "SMAX"
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    "name": "vmax_u16",
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      "uint16x4_t b"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A32",
      "A64"
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        "UMAX"
      ]
    ]
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    "SIMD_ISA": "Neon",
    "name": "vmax_u32",
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      "uint32x2_t b"
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        "register": "Vn.2S"
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      "A64"
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      "uint8x8_t a",
      "uint8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
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      "A64"
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        "UMAX"
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    "SIMD_ISA": "Neon",
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      "float16_t a",
      "float16_t b"
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      "value": "float16_t"
    },
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      "a": {
        "register": "Hn"
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        "register": "Hm"
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        "FMAX"
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  {
    "SIMD_ISA": "Neon",
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      "float16x4_t b"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
    ],
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        "FMAXNM"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
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      "A64"
    ],
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        "FMAXNM"
      ]
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    "SIMD_ISA": "Neon",
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      "float64x1_t b"
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        "register": "Dn"
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      "b": {
        "register": "Dm"
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        "FMAXNM"
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    "SIMD_ISA": "Neon",
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      "float16_t b"
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      "value": "float16_t"
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        "register": "Hn"
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      "b": {
        "register": "Hm"
      }
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      "A64"
    ],
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        "FMAXNM"
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    "SIMD_ISA": "Neon",
    "name": "vmaxnmq_f16",
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      "float16x8_t b"
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      "value": "float16x8_t"
    },
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
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      "A64"
    ],
    "instructions": [
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        "FMAXNM"
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    "SIMD_ISA": "Neon",
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      "float32x4_t b"
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      "value": "float32x4_t"
    },
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        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
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      "A64"
    ],
    "instructions": [
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        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmv_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
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      "A64"
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      [
        "FMAXNMP"
      ]
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  },
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    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float32_t"
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      "a": {
        "register": "Vn.2S"
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      "A64"
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        "FMAXNMP"
      ]
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  },
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    "SIMD_ISA": "Neon",
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      "value": "float16_t"
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      "a": {
        "register": "Vn.8H"
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        "FMAXNMP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "float32_t"
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      "a": {
        "register": "Vn.4S"
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        "FMAXNMV"
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    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "value": "float64_t"
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        "register": "Vn.2D"
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        "FMAXNMP"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t b"
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      "a": {
        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A64"
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      [
        "FMAX"
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "FMAX"
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t b"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      [
        "FMAX"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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      [
        "SMAX"
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "SMAX"
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    "SIMD_ISA": "Neon",
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      "int8x16_t b"
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      "value": "int8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
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        "SMAX"
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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      [
        "UMAX"
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  {
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      "uint32x4_t b"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "UMAX"
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      "uint8x16_t b"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
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        "UMAX"
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      "value": "float16_t"
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        "register": "Vn.4H"
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        "FMAXP"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2S"
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        "FMAXP"
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      "value": "int16_t"
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        "register": "Vn.4H"
      }
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        "SMAXV"
      ]
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      "value": "int32_t"
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        "register": "Vm.2S"
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        "SMAXP"
      ]
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      "int8x8_t a"
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      "value": "int8_t"
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        "register": "Vn.8B"
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        "SMAXV"
      ]
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        "register": "Vn.4H"
      }
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        "UMAXV"
      ]
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  {
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        "register": "Vm.2S"
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        "UMAXP"
      ]
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        "register": "Vn.8B"
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        "UMAXV"
      ]
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        "register": "Vn.8H"
      }
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      [
        "FMAXP"
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        "register": "Vn.4S"
      }
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        "FMAXV"
      ]
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        "register": "Vn.2D"
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        "FMAXP"
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        "register": "Vn.8H"
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        "SMAXV"
      ]
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        "register": "Vn.4S"
      }
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        "SMAXV"
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        "register": "Vn.16B"
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        "SMAXV"
      ]
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        "register": "Vn.8H"
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        "UMAXV"
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    "SIMD_ISA": "Neon",
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      "uint32x4_t a"
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      "value": "uint32_t"
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        "register": "Vn.4S"
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        "UMAXV"
      ]
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    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.16B"
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      [
        "UMAXV"
      ]
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    "SIMD_ISA": "Neon",
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      "float16x4_t b"
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      "value": "float16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
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      [
        "FMIN"
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      "value": "float32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A64"
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        "FMIN"
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    "SIMD_ISA": "Neon",
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      "float64x1_t b"
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      "value": "float64x1_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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        "FMIN"
      ]
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    "SIMD_ISA": "Neon",
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "SMIN"
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    "SIMD_ISA": "Neon",
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      "value": "int32x2_t"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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        "SMIN"
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    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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        "SMIN"
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    "SIMD_ISA": "Neon",
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "UMIN"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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        "UMIN"
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    "SIMD_ISA": "Neon",
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      "uint8x8_t b"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A32",
      "A64"
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        "UMIN"
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    "SIMD_ISA": "Neon",
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      "float16_t b"
    ],
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      "value": "float16_t"
    },
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      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
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    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnm_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
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      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmv_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmv_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmvq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminnmvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "result"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmmlaq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmmlaq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f16",
    "arguments": [
      "float16_t value"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f32",
    "arguments": [
      "float32_t value"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f64",
    "arguments": [
      "float64_t value"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_p16",
    "arguments": [
      "poly16_t value"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_p8",
    "arguments": [
      "poly8_t value"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s16",
    "arguments": [
      "int16_t value"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s32",
    "arguments": [
      "int32_t value"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s64",
    "arguments": [
      "int64_t value"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s8",
    "arguments": [
      "int8_t value"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u16",
    "arguments": [
      "uint16_t value"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u32",
    "arguments": [
      "uint32_t value"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u64",
    "arguments": [
      "uint64_t value"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u8",
    "arguments": [
      "uint8_t value"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f16",
    "arguments": [
      "float16_t value"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f32",
    "arguments": [
      "float32_t value"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f64",
    "arguments": [
      "float64_t value"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_p16",
    "arguments": [
      "poly16_t value"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_p8",
    "arguments": [
      "poly8_t value"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s16",
    "arguments": [
      "int16_t value"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s32",
    "arguments": [
      "int32_t value"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s64",
    "arguments": [
      "int64_t value"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s8",
    "arguments": [
      "int8_t value"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u16",
    "arguments": [
      "uint16_t value"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u32",
    "arguments": [
      "uint32_t value"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u64",
    "arguments": [
      "uint64_t value"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u8",
    "arguments": [
      "uint8_t value"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuld_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuld_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_p64",
    "arguments": [
      "poly64_t a",
      "poly64_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.1D"
      },
      "b": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuls_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuls_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvnq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vneg_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vnegq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorn_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "ORN"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "uint8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "ORN"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A64"
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      [
        "ORN"
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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      [
        "ORN"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t b"
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        "register": "Vn.16B"
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      [
        "ORN"
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  {
    "SIMD_ISA": "Neon",
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      "A32",
      "A64"
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      [
        "ORN"
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    "SIMD_ISA": "Neon",
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      "value": "uint16x8_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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      [
        "ORN"
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      "value": "uint32x4_t"
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      "A64"
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      [
        "ORN"
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    "SIMD_ISA": "Neon",
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      "uint64x2_t b"
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      "value": "uint64x2_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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      [
        "ORN"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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        "ORN"
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    "SIMD_ISA": "Neon",
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      "int16x4_t b"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "ORR"
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      "int32x2_t b"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "ORR"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "ORR"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A32",
      "A64"
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        "ORR"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "ORR"
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    "SIMD_ISA": "Neon",
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      "uint32x2_t b"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "ORR"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "ORR"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "ORR"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "ORR"
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    "SIMD_ISA": "Neon",
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        "ORR"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "ORR"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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        "ORR"
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      "A64"
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        "register": "Vd.1D"
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        "register": "Vd.4H"
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        "register": "Vn.8B"
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        "register": "Vn.4H"
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      "A64"
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    "SIMD_ISA": "Neon",
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        "register": "Vd.1D"
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        "register": "Vn.2S"
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      "A32",
      "A64"
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        "UADALP"
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    "SIMD_ISA": "Neon",
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        "register": "Vd.4H"
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        "register": "Vn.8B"
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      "A32",
      "A64"
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        "UADALP"
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    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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        "register": "Vd.4S"
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        "register": "Vn.8H"
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int64x2_t"
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        "register": "Vd.2D"
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        "register": "Vn.4S"
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      "A32",
      "A64"
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        "SADALP"
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    "SIMD_ISA": "Neon",
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      "int8x16_t b"
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      "value": "int16x8_t"
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        "register": "Vd.8H"
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        "register": "Vn.16B"
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      "A32",
      "A64"
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        "SADALP"
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    "SIMD_ISA": "Neon",
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      "value": "uint32x4_t"
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        "register": "Vd.4S"
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      "b": {
        "register": "Vn.8H"
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      "A32",
      "A64"
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        "UADALP"
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    "SIMD_ISA": "Neon",
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      "uint32x4_t b"
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      "value": "uint64x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
        "register": "Vn.4S"
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      "A32",
      "A64"
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        "UADALP"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t a",
      "uint8x16_t b"
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      "value": "uint16x8_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadds_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnms_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxs_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnms_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmins_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsb_s8",
    "arguments": [
      "int8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabss_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddb_u8",
    "arguments": [
      "uint8_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddh_u16",
    "arguments": [
      "uint16_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadds_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadds_u32",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_lane_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_laneq_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_lane_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_laneq_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_lane_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_laneq_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_lane_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_laneq_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnd_u64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnh_u16",
    "arguments": [
      "uint16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovns_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovns_u32",
    "arguments": [
      "uint32_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s16",
    "arguments": [
      "uint8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s32",
    "arguments": [
      "uint16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s64",
    "arguments": [
      "uint32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovund_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovunh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovuns_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegb_s8",
    "arguments": [
      "int8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegs_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u64",
    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlb_u8",
    "arguments": [
      "uint8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshld_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshld_u64",
    "arguments": [
      "uint64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlh_u16",
    "arguments": [
      "uint16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u16",
    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshls_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshls_u32",
    "arguments": [
      "uint32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnd_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnd_n_u64",
    "arguments": [
      "uint64_t a",
      "const int n"
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    "return_type": {
      "value": "uint32_t"
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      "a": {
        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnh_n_s16",
    "arguments": [
      "int16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnh_n_u16",
    "arguments": [
      "uint16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8_t"
    },
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      "a": {
        "register": "Hn"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrns_n_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
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      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrns_n_u32",
    "arguments": [
      "uint32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_high_n_s16",
    "arguments": [
      "uint8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_high_n_s32",
    "arguments": [
      "uint16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_high_n_s64",
    "arguments": [
      "uint32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrund_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrunh_n_s16",
    "arguments": [
      "int16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshruns_n_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_s16",
    "arguments": [
      "int16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_s32",
    "arguments": [
      "int32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_s64",
    "arguments": [
      "int64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_s8",
    "arguments": [
      "int8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_u16",
    "arguments": [
      "uint16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_u32",
    "arguments": [
      "uint32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_u64",
    "arguments": [
      "uint64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_n_u8",
    "arguments": [
      "uint8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
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      "value": "int32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_s8",
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      "int8x8_t a",
      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_u32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_u64",
    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "int8x8_t b"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int8_t a",
      "const int n"
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      "value": "int8_t"
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      "a": {
        "register": "Bn"
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      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8_t a",
      "const int n"
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      "value": "uint8_t"
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        "register": "Bn"
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      "n": {
        "minimum": 0,
        "maximum": 7
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      "A64"
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      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshlb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
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      "value": "int8_t"
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      "a": {
        "register": "Bn"
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      "b": {
        "register": "Bm"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8_t a",
      "int8_t b"
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      "value": "uint8_t"
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      "a": {
        "register": "Bn"
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      "b": {
        "register": "Bm"
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    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshld_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
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      "value": "int64_t"
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        "register": "Dn"
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      "n": {
        "minimum": 0,
        "maximum": 63
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64_t a",
      "const int n"
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      "value": "uint64_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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    "instructions": [
      [
        "UQSHL"
      ]
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    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "int64_t"
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        "register": "Dn"
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        "register": "Dm"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint64_t a",
      "int64_t b"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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    "instructions": [
      [
        "UQSHL"
      ]
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      "int16_t a",
      "const int n"
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      "value": "int16_t"
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        "register": "Hn"
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        "maximum": 15
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      [
        "SQSHL"
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    "SIMD_ISA": "Neon",
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        "maximum": 15
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        "UQSHL"
      ]
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    "SIMD_ISA": "Neon",
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      "int16_t b"
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        "register": "Hn"
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        "register": "Hm"
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    "instructions": [
      [
        "SQSHL"
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    "SIMD_ISA": "Neon",
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      "int16_t b"
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      "value": "uint16_t"
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        "register": "Hn"
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      "b": {
        "register": "Hm"
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      [
        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
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      "value": "int16x8_t"
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        "register": "Vn.8H"
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      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a",
      "const int n"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "minimum": 0,
        "maximum": 31
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a",
      "const int n"
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      "value": "int64x2_t"
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        "register": "Vn.2D"
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        "minimum": 0,
        "maximum": 63
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a",
      "const int n"
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        "register": "Vn.16B"
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        "maximum": 7
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      "A64"
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    "instructions": [
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        "SQSHL"
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    "SIMD_ISA": "Neon",
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        "maximum": 15
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      "A64"
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        "UQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
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        "minimum": 0,
        "maximum": 31
      }
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      "A32",
      "A64"
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    "instructions": [
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        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint64x2_t"
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        "register": "Vn.2D"
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        "minimum": 0,
        "maximum": 63
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      "A32",
      "A64"
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        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "minimum": 0,
        "maximum": 7
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      "A32",
      "A64"
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    "instructions": [
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        "UQSHL"
      ]
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    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A64"
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        "SQSHL"
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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      "A64"
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        "SQSHL"
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    "SIMD_ISA": "Neon",
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      "int64x2_t b"
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      "value": "int64x2_t"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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      "A64"
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        "SQSHL"
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    "SIMD_ISA": "Neon",
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      "int8x16_t b"
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      "value": "int8x16_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A32",
      "A64"
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        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
    ],
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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        "UQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
      "int32x4_t b"
    ],
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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    "instructions": [
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        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqshlq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
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    "return_type": {
      "value": "uint64x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t a",
      "int8x16_t b"
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    "return_type": {
      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshls_n_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshls_n_u32",
    "arguments": [
      "uint32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
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      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshls_s32",
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      "int32_t a",
      "int32_t b"
    ],
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      "value": "int32_t"
    },
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      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
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    "instructions": [
      [
        "SQSHL"
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32_t a",
      "int32_t b"
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      "value": "uint32_t"
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      "a": {
        "register": "Sn"
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      "b": {
        "register": "Sm"
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    },
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    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a",
      "const int n"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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        "minimum": 0,
        "maximum": 15
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHLU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a",
      "const int n"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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        "minimum": 0,
        "maximum": 31
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHLU"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a",
      "const int n"
    ],
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      "value": "uint64x1_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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      "A32",
      "A64"
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      [
        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "const int n"
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
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        "maximum": 7
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      "A64"
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    "instructions": [
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int8_t a",
      "const int n"
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      "value": "uint8_t"
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      "a": {
        "register": "Bn"
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        "minimum": 0,
        "maximum": 7
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    "instructions": [
      [
        "SQSHLU"
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int64_t a",
      "const int n"
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      "value": "uint64_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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    "instructions": [
      [
        "SQSHLU"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int16_t a",
      "const int n"
    ],
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      "value": "uint16_t"
    },
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        "register": "Hn"
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        "minimum": 0,
        "maximum": 15
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    "instructions": [
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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        "maximum": 15
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a",
      "const int n"
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
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        "minimum": 0,
        "maximum": 31
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      "A64"
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a",
      "const int n"
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      "value": "uint64x2_t"
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        "register": "Vn.2D"
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        "maximum": 63
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      "A64"
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a",
      "const int n"
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      "value": "uint8x16_t"
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        "register": "Vn.16B"
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int32_t a",
      "const int n"
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      "value": "uint32_t"
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        "register": "Sn"
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        "maximum": 31
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        "SQSHLU"
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t r",
      "int16x8_t a",
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        "register": "Vn.8H"
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        "maximum": 8
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        "register": "Vd.8B"
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        "SQSHRN2"
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      "int32x4_t a",
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        "register": "Vn.4S"
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        "maximum": 16
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        "register": "Vd.4H"
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        "SQSHRN2"
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      "int64x2_t a",
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        "register": "Vn.2D"
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        "maximum": 32
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        "register": "Vd.2S"
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        "SQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t r",
      "uint16x8_t a",
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        "register": "Vn.8H"
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        "maximum": 8
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        "register": "Vd.8B"
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        "UQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
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        "register": "Vn.4S"
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        "maximum": 16
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        "register": "Vd.4H"
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        "UQSHRN2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint64x2_t a",
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        "register": "Vn.2D"
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        "maximum": 32
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        "register": "Vd.2S"
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        "UQSHRN2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "maximum": 8
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      "A64"
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        "SQSHRN"
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  {
    "SIMD_ISA": "Neon",
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        "maximum": 16
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      "A64"
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    "instructions": [
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        "SQSHRN"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int32x2_t"
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        "register": "Vn.2D"
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        "maximum": 32
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "maximum": 8
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      "A64"
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        "UQSHRN"
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  {
    "SIMD_ISA": "Neon",
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        "maximum": 16
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      "A64"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint32x2_t"
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        "register": "Vn.2D"
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        "maximum": 32
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      "A64"
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    "SIMD_ISA": "Neon",
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      "const int n"
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        "register": "Dn"
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        "maximum": 32
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        "SQSHRN"
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  {
    "SIMD_ISA": "Neon",
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    "instructions": [
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        "UQSHRN"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int8_t"
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        "register": "Hn"
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        "maximum": 8
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        "SQSHRN"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Hn"
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        "maximum": 8
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        "UQSHRN"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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        "register": "Sn"
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        "maximum": 16
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        "SQSHRN"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Sn"
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        "maximum": 16
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        "UQSHRN"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
      "const int n"
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      "value": "uint8x16_t"
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        "register": "Vn.8H"
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        "maximum": 8
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        "register": "Vd.8B"
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        "SQSHRUN2"
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    "SIMD_ISA": "Neon",
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      "int32x4_t a",
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        "register": "Vn.4S"
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        "maximum": 16
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        "register": "Vd.4H"
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        "SQSHRUN2"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a",
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      "value": "uint32x4_t"
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        "register": "Vn.2D"
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        "maximum": 32
      },
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        "register": "Vd.2S"
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    "instructions": [
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        "SQSHRUN2"
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    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x8_t a",
      "const int n"
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      "value": "uint8x8_t"
    },
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        "register": "Vn.8H"
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        "minimum": 1,
        "maximum": 8
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    },
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHRUN"
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  {
    "SIMD_ISA": "Neon",
    "name": "vqshrun_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
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    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshrun_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshrund_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshrunh_n_s16",
    "arguments": [
      "int16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshruns_n_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
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    "return_type": {
      "value": "int8x8_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
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    "return_type": {
      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
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      "value": "int8_t"
    },
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      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubb_u8",
    "arguments": [
      "uint8_t a",
      "uint8_t b"
    ],
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      "value": "uint8_t"
    },
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      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
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      "value": "int64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
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      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
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      "value": "int16_t"
    },
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      "a": {
        "register": "Hn"
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      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubh_u16",
    "arguments": [
      "uint16_t a",
      "uint16_t b"
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      "value": "uint16_t"
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      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
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    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubs_u32",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
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      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1_p8",
    "arguments": [
      "poly8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1_u8",
    "arguments": [
      "uint8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_p8",
    "arguments": [
      "poly8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_s8",
    "arguments": [
      "int8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_u8",
    "arguments": [
      "uint8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_p8",
    "arguments": [
      "poly8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_s8",
    "arguments": [
      "int8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_u8",
    "arguments": [
      "uint8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2q_p8",
    "arguments": [
      "poly8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
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      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_s8",
    "arguments": [
      "int8x8_t a",
      "int8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t.val[0]": {
        "register": "Vn.16B"
      },
      "t.val[1]": {
        "register": "Vn+1.16B"
      },
      "t.val[2]": {
        "register": "Vn+2.16B"
      },
      "t.val[3]": {
        "register": "Vn+3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrax1q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RAX1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecped_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpes_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpss_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxd_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p64",
    "arguments": [
      "poly64x1_t a"
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    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p8",
    "arguments": [
      "poly8x8_t a"
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    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s32",
    "arguments": [
      "int32x2_t a"
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    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f16",
    "arguments": [
      "float16x4_t a"
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    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f32",
    "arguments": [
      "float32x2_t a"
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    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s16",
    "arguments": [
      "int16x4_t a"
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      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s32",
    "arguments": [
      "int32x2_t a"
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    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f32",
    "arguments": [
      "float32x2_t a"
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    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u64",
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      "uint64x2_t a"
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vd.2D"
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    },
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      "v7",
      "A32",
      "A64"
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      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16_p8",
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      "value": "poly8x8_t"
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        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
    ],
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      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16_s8",
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      "int8x8_t vec"
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      "vec": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
    ],
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      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t vec"
    ],
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      "value": "uint8x8_t"
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      "vec": {
        "register": "Vn.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
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      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16q_p8",
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      "poly8x16_t vec"
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      "vec": {
        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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      [
        "REV16"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev16q_s8",
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      "int8x16_t vec"
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      "value": "int8x16_t"
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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      [
        "REV16"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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      [
        "REV16"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_p16",
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      "value": "poly16x4_t"
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      "vec": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_p8",
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      "poly8x8_t vec"
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      "vec": {
        "register": "Vn.8B"
      }
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      "A32",
      "A64"
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      [
        "REV32"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x4_t vec"
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        "register": "Vn.4H"
      }
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      "A32",
      "A64"
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        "REV32"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "vec": {
        "register": "Vn.8B"
      }
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      "A32",
      "A64"
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        "REV32"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.4H"
      }
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      "A32",
      "A64"
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        "REV32"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint8x8_t"
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      "vec": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
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        "REV32"
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    "SIMD_ISA": "Neon",
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      "value": "poly16x8_t"
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        "register": "Vn.8H"
      }
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      "A32",
      "A64"
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        "REV32"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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        "REV32"
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        "register": "Vn.8H"
      }
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      "A32",
      "A64"
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        "REV32"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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    "instructions": [
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        "REV32"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_u16",
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      "uint16x8_t vec"
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      "value": "uint16x8_t"
    },
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      "vec": {
        "register": "Vn.8H"
      }
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      "A32",
      "A64"
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        "REV32"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_u8",
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      "value": "uint8x16_t"
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
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        "REV32"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_f16",
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      "value": "float16x4_t"
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      "vec": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
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        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_p16",
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      "vec": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_p8",
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      "poly8x8_t vec"
    ],
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        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_s16",
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        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_s32",
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        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "REV64"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_s8",
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      "int8x8_t vec"
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      "value": "int8x8_t"
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      "vec": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_u16",
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    ],
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    },
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      "vec": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_u32",
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      "uint32x2_t vec"
    ],
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      "value": "uint32x2_t"
    },
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        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
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        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_u8",
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      "uint8x8_t vec"
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      "value": "uint8x8_t"
    },
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      "vec": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "REV64"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_f16",
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    ],
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      "value": "float16x8_t"
    },
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
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        "REV64"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_f32",
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      "float32x4_t vec"
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    },
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        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
    ],
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        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_p16",
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
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        "REV64"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_p8",
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        "register": "Vn.16B"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
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        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_s16",
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      "int16x8_t vec"
    ],
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      "value": "int16x8_t"
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_s32",
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    ],
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      "value": "int32x4_t"
    },
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        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
    ],
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        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_s8",
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    ],
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      "value": "int8x16_t"
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        "register": "Vn.16B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_u16",
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      "uint16x8_t vec"
    ],
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_u32",
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      "uint32x4_t vec"
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrev64q_u8",
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        "register": "Vn.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrhadd_s16",
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      "int16x4_t b"
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      "value": "int16x4_t"
    },
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrhadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrhadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrhadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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        "URHADD"
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    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "uint32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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        "URHADD"
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    "SIMD_ISA": "Neon",
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      "uint8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A32",
      "A64"
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        "URHADD"
      ]
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    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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      [
        "SRHADD"
      ]
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "SRHADD"
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  {
    "SIMD_ISA": "Neon",
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      "int8x16_t b"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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        "SRHADD"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A32",
      "A64"
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        "URHADD"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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      "A32",
      "A64"
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        "URHADD"
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  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t b"
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      "value": "uint8x16_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A32",
      "A64"
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        "URHADD"
      ]
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      "float32x2_t a"
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      "value": "float32x2_t"
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      "a": {
        "register": "Vn"
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      [
        "FRINT32X"
      ]
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    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Dn"
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        "FRINT32X"
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    "SIMD_ISA": "Neon",
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn"
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        "FRINT32X"
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "value": "float64x2_t"
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        "register": "Vn"
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        "FRINT32X"
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  {
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      "value": "float32x2_t"
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      "a": {
        "register": "Vn"
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        "FRINT32Z"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Dn"
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      "A64"
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      [
        "FRINT32Z"
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  {
    "SIMD_ISA": "Neon",
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn"
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        "FRINT32Z"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn"
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        "FRINT32Z"
      ]
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  {
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      "a": {
        "register": "Vn"
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        "FRINT64X"
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  {
    "SIMD_ISA": "Neon",
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      "float64x1_t a"
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        "register": "Dn"
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        "FRINT64X"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn"
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        "FRINT64X"
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    "SIMD_ISA": "Neon",
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        "register": "Vn"
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        "FRINT64X"
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        "register": "Vn"
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        "FRINT64Z"
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        "register": "Dn"
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        "FRINT64Z"
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        "register": "Vn"
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        "FRINT64Z"
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      "float64x2_t a"
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        "register": "Vn"
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        "FRINT64Z"
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        "register": "Vn.4H"
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      "A64"
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        "FRINTZ"
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        "register": "Vn.2S"
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      "A64"
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        "FRINTZ"
      ]
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      "float64x1_t a"
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        "register": "Dn"
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        "FRINTZ"
      ]
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    "SIMD_ISA": "Neon",
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      "float16x4_t a"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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      "A64"
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        "FRINTA"
      ]
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    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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      "A64"
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        "FRINTA"
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      "float64x1_t a"
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        "register": "Dn"
      }
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        "FRINTA"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "float16_t"
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      "a": {
        "register": "Hn"
      }
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      "A64"
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        "FRINTA"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "float16x8_t"
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        "register": "Vn.8H"
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      "A64"
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        "FRINTA"
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      "value": "float32x4_t"
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        "register": "Vn.4S"
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      "A64"
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        "FRINTA"
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      "float64x2_t a"
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      "value": "float64x2_t"
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        "register": "Vn.2D"
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      [
        "FRINTA"
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "float16_t"
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      "a": {
        "register": "Hn"
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      "A64"
    ],
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      [
        "FRINTZ"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x4_t a"
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      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
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      [
        "FRINTI"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FRINTI"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrndi_f64",
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      "float64x1_t a"
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    },
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        "register": "Dn"
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    },
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    "instructions": [
      [
        "FRINTI"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "float16_t"
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        "register": "Hn"
      }
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      "A64"
    ],
    "instructions": [
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        "FRINTI"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vrndiq_f16",
    "arguments": [
      "float16x8_t a"
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      "value": "float16x8_t"
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      "a": {
        "register": "Vn.8H"
      }
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    "instructions": [
      [
        "FRINTI"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndiq_f32",
    "arguments": [
      "float32x4_t a"
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    "return_type": {
      "value": "float32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FRINTI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndiq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndm_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRINTM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndm_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRINTM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndm_f64",
    "arguments": [
      "float64x1_t a"
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    "return_type": {
      "value": "float64x1_t"
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      "a": {
        "register": "Dn"
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        "FRINTM"
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    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "float16_t"
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        "register": "Hn"
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        "FRINTM"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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      "A64"
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        "FRINTM"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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      "A64"
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        "FRINTM"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "FRINTM"
      ]
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.4H"
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      "A64"
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        "FRINTN"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2S"
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      "A64"
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        "FRINTN"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Dn"
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      "A64"
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        "FRINTN"
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    "SIMD_ISA": "Neon",
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        "register": "Hn"
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      "A64"
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        "FRINTN"
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      "value": "float16x8_t"
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        "register": "Vn.8H"
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      "A64"
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        "FRINTN"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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      "A64"
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        "FRINTN"
      ]
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        "register": "Vn.2D"
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      "A64"
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        "FRINTN"
      ]
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    "SIMD_ISA": "Neon",
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      "float32_t a"
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      "value": "float32_t"
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        "register": "Sn"
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      "A64"
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        "FRINTN"
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      "float16x4_t a"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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      "A32",
      "A64"
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      [
        "FRINTP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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      "A32",
      "A64"
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      [
        "FRINTP"
      ]
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    "SIMD_ISA": "Neon",
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      "float64x1_t a"
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      "value": "float64x1_t"
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        "register": "Dn"
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      "A64"
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      [
        "FRINTP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "float16_t"
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        "register": "Hn"
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      "A64"
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      [
        "FRINTP"
      ]
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  {
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      "float16x8_t a"
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      "value": "float16x8_t"
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        "register": "Vn.8H"
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      "A64"
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      [
        "FRINTP"
      ]
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    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "A32",
      "A64"
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      [
        "FRINTP"
      ]
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    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "value": "float64x2_t"
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        "register": "Vn.2D"
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      "A64"
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      [
        "FRINTP"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a"
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        "register": "Vn.8H"
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      "A32",
      "A64"
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      [
        "FRINTZ"
      ]
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    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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        "register": "Vn.4S"
      }
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      "A64"
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      [
        "FRINTZ"
      ]
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      "float64x2_t a"
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      "value": "float64x2_t"
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        "register": "Vn.2D"
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      "A64"
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      [
        "FRINTZ"
      ]
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    "SIMD_ISA": "Neon",
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      "float16x4_t a"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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      "A64"
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        "FRINTX"
      ]
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    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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      "A64"
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        "FRINTX"
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        "register": "Dn"
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        "FRINTX"
      ]
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      "float16_t a"
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        "register": "Hn"
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      "A64"
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        "FRINTX"
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  {
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      "float16x8_t a"
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        "register": "Vn.8H"
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      "A64"
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        "FRINTX"
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        "register": "Vn.4S"
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      "A64"
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        "FRINTX"
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        "register": "Vn.2D"
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        "FRINTX"
      ]
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      "int16x4_t b"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "SRSHL"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "A32",
      "A64"
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        "SRSHL"
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      "int64x1_t b"
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        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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      "int8x8_t b"
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      "value": "int8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "SRSHL"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "URSHL"
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    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "A32",
      "A64"
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        "URSHL"
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    "SIMD_ISA": "Neon",
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      "int64x1_t b"
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      "value": "uint64x1_t"
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        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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        "URSHL"
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A32",
      "A64"
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        "URSHL"
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    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "int64_t"
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        "register": "Dn"
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        "register": "Dm"
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        "SRSHL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
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      [
        "URSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
    ],
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      "value": "int16x8_t"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A32",
      "A64"
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    "instructions": [
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        "SRSHL"
      ]
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
    ],
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      "value": "int32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u16",
    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s16",
    "arguments": [
      "int16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s32",
    "arguments": [
      "int32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s64",
    "arguments": [
      "int64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s8",
    "arguments": [
      "int8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u16",
    "arguments": [
      "uint16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u32",
    "arguments": [
      "uint32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u64",
    "arguments": [
      "uint64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u8",
    "arguments": [
      "uint8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrd_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrd_n_u64",
    "arguments": [
      "uint64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "32(Vd)"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s8",
    "arguments": [
      "int8x16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrted_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtes_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtss_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsrad_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsrad_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vscale_f16",
    "arguments": [
      "float16x4_t vn",
      "int16x4_t vm"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4H"
      },
      "vn": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSCALE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vscale_f32",
    "arguments": [
      "float32x2_t vn",
      "int32x2_t vm"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2S"
      },
      "vn": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSCALE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vscaleq_f16",
    "arguments": [
      "float16x8_t vn",
      "int16x8_t vm"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.8H"
      },
      "vn": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSCALE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vscaleq_f32",
    "arguments": [
      "float32x4_t vn",
      "int32x4_t vm"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.4S"
      },
      "vn": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSCALE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vscaleq_f64",
    "arguments": [
      "float64x2_t vn",
      "int64x2_t vm"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "vm": {
        "register": "Vm.2D"
      },
      "vn": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSCALE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "VnH"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p16",
    "arguments": [
      "poly16_t a",
      "poly16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p64",
    "arguments": [
      "poly64_t a",
      "poly64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p8",
    "arguments": [
      "poly8_t a",
      "poly8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s64",
    "arguments": [
      "int64_t a",
      "int64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s8",
    "arguments": [
      "int8_t a",
      "int8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u16",
    "arguments": [
      "uint16_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u32",
    "arguments": [
      "uint32_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u64",
    "arguments": [
      "uint64_t a",
      "uint64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u8",
    "arguments": [
      "uint8_t a",
      "uint8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "VnH"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p16",
    "arguments": [
      "poly16_t a",
      "poly16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p64",
    "arguments": [
      "poly64_t a",
      "poly64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p8",
    "arguments": [
      "poly8_t a",
      "poly8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s64",
    "arguments": [
      "int64_t a",
      "int64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s8",
    "arguments": [
      "int8_t a",
      "int8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u16",
    "arguments": [
      "uint16_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u32",
    "arguments": [
      "uint32_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u64",
    "arguments": [
      "uint64_t a",
      "uint64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u8",
    "arguments": [
      "uint8_t a",
      "uint8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1cq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1C"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1h_u32",
    "arguments": [
      "uint32_t hash_e"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "hash_e": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1mq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1M"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1pq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1P"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1su0q_u32",
    "arguments": [
      "uint32x4_t w0_3",
      "uint32x4_t w4_7",
      "uint32x4_t w8_11"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "w0_3": {
        "register": "Vd.4S"
      },
      "w4_7": {
        "register": "Vn.4S"
      },
      "w8_11": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1su1q_u32",
    "arguments": [
      "uint32x4_t tw0_3",
      "uint32x4_t w12_15"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "tw0_3": {
        "register": "Vd.4S"
      },
      "w12_15": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256h2q_u32",
    "arguments": [
      "uint32x4_t hash_efgh",
      "uint32x4_t hash_abcd",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qn"
      },
      "hash_efgh": {
        "register": "Qd"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256H2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256hq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32x4_t hash_efgh",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_efgh": {
        "register": "Qn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256su0q_u32",
    "arguments": [
      "uint32x4_t w0_3",
      "uint32x4_t w4_7"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "w0_3": {
        "register": "Vd.4S"
      },
      "w4_7": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256su1q_u32",
    "arguments": [
      "uint32x4_t tw0_3",
      "uint32x4_t w8_11",
      "uint32x4_t w12_15"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "tw0_3": {
        "register": "Vd.4S"
      },
      "w12_15": {
        "register": "Vm.4S"
      },
      "w8_11": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512h2q_u64",
    "arguments": [
      "uint64x2_t sum_ab",
      "uint64x2_t hash_c_",
      "uint64x2_t hash_ab"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "hash_ab": {
        "register": "Vm.2D"
      },
      "hash_c_": {
        "register": "Qn"
      },
      "sum_ab": {
        "register": "Qd"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512H2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512hq_u64",
    "arguments": [
      "uint64x2_t hash_ed",
      "uint64x2_t hash_gf",
      "uint64x2_t kwh_kwh2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "hash_ed": {
        "register": "Qd"
      },
      "hash_gf": {
        "register": "Qn"
      },
      "kwh_kwh2": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512su0q_u64",
    "arguments": [
      "uint64x2_t w0_1",
      "uint64x2_t w2_"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "w0_1": {
        "register": "Vd.2D"
      },
      "w2_": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512su1q_u64",
    "arguments": [
      "uint64x2_t s01_s02",
      "uint64x2_t w14_15",
      "uint64x2_t w9_10"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "s01_s02": {
        "register": "Vd.2D"
      },
      "w14_15": {
        "register": "Vn.2D"
      },
      "w9_10": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s16",
    "arguments": [
      "int16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s32",
    "arguments": [
      "int32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s64",
    "arguments": [
      "int64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s8",
    "arguments": [
      "int8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u16",
    "arguments": [
      "uint16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u32",
    "arguments": [
      "uint32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u64",
    "arguments": [
      "uint64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u8",
    "arguments": [
      "uint8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
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      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "int8x8_t b"
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      "value": "int8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "SSHL"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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        "USHL"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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        "USHL"
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  {
    "SIMD_ISA": "Neon",
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      "int64x1_t b"
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      "value": "uint64x1_t"
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        "register": "Dn"
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        "register": "Dm"
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      "A64"
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        "USHL"
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "USHL"
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    "SIMD_ISA": "Neon",
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      "const int n"
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        "SHL"
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  {
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        "SHL"
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      "int64_t b"
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      "value": "int64_t"
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        "register": "Dn"
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        "register": "Dm"
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      [
        "SSHL"
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  {
    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "uint64_t"
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        "register": "Dn"
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        "register": "Dm"
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        "USHL"
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        "register": "Vn.8H"
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        "maximum": 16
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        "SSHLL2"
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      "value": "int64x2_t"
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        "register": "Vn.4S"
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        "maximum": 32
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        "SSHLL2"
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        "register": "Vn.16B"
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        "SSHLL2"
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  {
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        "USHLL2"
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        "USHLL2"
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        "USHLL2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "USHL"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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      "A64"
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        "USHL"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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        "USHL"
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    "SIMD_ISA": "Neon",
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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    "SIMD_ISA": "Neon",
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      "value": "int32x2_t"
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  {
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  {
    "SIMD_ISA": "Neon",
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        "USHR"
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  {
    "SIMD_ISA": "Neon",
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  {
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        "USHR"
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        "USHR"
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        "SSHR"
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  {
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        "USHR"
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        "SHRN2"
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      "poly16x4_t b",
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        "register": "Vd.2S"
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      "int64x1_t b",
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      "value": "int64x1_t"
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        "register": "Dd"
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      "b": {
        "register": "Dn"
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        "maximum": 63
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      "int8x8_t b",
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    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsli_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsli_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsli_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsli_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vslid_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vslid_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
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        "minimum": 0,
        "maximum": 7
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
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        "minimum": 0,
        "maximum": 15
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    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsliq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SLI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3partw1q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3PARTW1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3partw2q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3PARTW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3ss1q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "c": {
        "register": "Va.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3SS1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt1aq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      },
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT1A"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt1bq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      },
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT1B"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt2aq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      },
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT2A"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt2bq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      },
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm4ekeyq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM4EKEY"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm4eq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM4E"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u64",
    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddb_u8",
    "arguments": [
      "uint8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bd"
      },
      "b": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddd_u64",
    "arguments": [
      "uint64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddh_u16",
    "arguments": [
      "uint16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
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      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadds_u32",
    "arguments": [
      "uint32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      }
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    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f16",
    "arguments": [
      "float16x4_t a"
    ],
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      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A64"
    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f32",
    "arguments": [
      "float32x2_t a"
    ],
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      "value": "float32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
      }
    },
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      "A64"
    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f64",
    "arguments": [
      "float64x1_t a"
    ],
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      "value": "float64x1_t"
    },
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      "a": {
        "register": "Dn"
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    },
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      "A64"
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrth_f16",
    "arguments": [
      "float16_t a"
    ],
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      "value": "float16_t"
    },
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      "a": {
        "register": "Hn"
      }
    },
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      "A64"
    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrtq_f16",
    "arguments": [
      "float16x8_t a"
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      "value": "float16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
    },
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      "A64"
    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrtq_f32",
    "arguments": [
      "float32x4_t a"
    ],
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      "value": "float32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrtq_f64",
    "arguments": [
      "float64x2_t a"
    ],
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      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
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      "A64"
    ],
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      [
        "FSQRT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
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      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
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        "minimum": 1,
        "maximum": 32
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
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      "value": "int64x1_t"
    },
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      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
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        "minimum": 1,
        "maximum": 64
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
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        "minimum": 1,
        "maximum": 8
      }
    },
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      "A32",
      "A64"
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      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
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        "minimum": 1,
        "maximum": 32
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
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        "minimum": 1,
        "maximum": 8
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrad_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrad_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
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      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
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        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
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        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
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        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
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        "minimum": 1,
        "maximum": 8
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
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        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
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        "minimum": 1,
        "maximum": 32
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
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        "minimum": 1,
        "maximum": 64
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
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        "minimum": 1,
        "maximum": 8
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
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      "A64"
    ],
    "instructions": [
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        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrid_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrid_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x2",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x3",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x4",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x2",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x3",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x4",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x2",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x3",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x4",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_mf8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x2",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x3",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x4",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x2",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x3",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x4",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x2",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x3",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x4",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x2",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x3",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x4",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x2",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x3",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x4",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x2",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x3",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x4",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x2",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x3",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x2",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x3",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x4",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x2",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x3",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x4",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x2",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x3",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x4",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x2",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x3",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x4",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x2",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x3",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x4",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x2",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x3",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x4",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x2",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x3",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x4",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_mf8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x2",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x3",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x4",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x2",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x3",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x4",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x2",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x3",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x4",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x2",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x3",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x4",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x2",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x3",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x4",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x2",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x3",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x4",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x2",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x3",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x2",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x3",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x4",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x2",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x3",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x4",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x2",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x3",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x4",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x2",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x3",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x4",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4H"
      },
      "val.val[1]": {
        "register": "Vt2.4H"
      },
      "val.val[2]": {
        "register": "Vt3.4H"
      },
      "val.val[3]": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2S"
      },
      "val.val[1]": {
        "register": "Vt2.2S"
      },
      "val.val[2]": {
        "register": "Vt3.2S"
      },
      "val.val[3]": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.1D"
      },
      "val.val[1]": {
        "register": "Vt2.1D"
      },
      "val.val[2]": {
        "register": "Vt3.1D"
      },
      "val.val[3]": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8B"
      },
      "val.val[1]": {
        "register": "Vt2.8B"
      },
      "val.val[2]": {
        "register": "Vt3.8B"
      },
      "val.val[3]": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.8H"
      },
      "val.val[1]": {
        "register": "Vt2.8H"
      },
      "val.val[2]": {
        "register": "Vt3.8H"
      },
      "val.val[3]": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.4S"
      },
      "val.val[1]": {
        "register": "Vt2.4S"
      },
      "val.val[2]": {
        "register": "Vt3.4S"
      },
      "val.val[3]": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.2D"
      },
      "val.val[1]": {
        "register": "Vt2.2D"
      },
      "val.val[2]": {
        "register": "Vt3.2D"
      },
      "val.val[3]": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val.val[0]": {
        "register": "Vt.16B"
      },
      "val.val[1]": {
        "register": "Vt2.16B"
      },
      "val.val[2]": {
        "register": "Vt3.16B"
      },
      "val.val[3]": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstl1q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "STL1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstrq_p128",
    "arguments": [
      "poly128_t * ptr",
      "poly128_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Qt"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "STR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsudot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsudot_laneq_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
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      "r": {
        "register": "Vd.2S"
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    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUDOT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsudotq_lane_s32",
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      "int32x4_t r",
      "int8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
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      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
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        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUDOT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t r",
      "int8x16_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
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      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
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        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl1_p8",
    "arguments": [
      "poly8x8_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):a": {
        "register": "Vn.16B"
      },
      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t idx"
    ],
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      "value": "int8x8_t"
    },
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      "Zeros(64):a": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
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      [
        "TBL"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtbl1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):a": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl2_p8",
    "arguments": [
      "poly8x8x2_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl2_s8",
    "arguments": [
      "int8x8x2_t a",
      "int8x8_t idx"
    ],
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      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl2_u8",
    "arguments": [
      "uint8x8x2_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtbl3_p8",
    "arguments": [
      "poly8x8x3_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):a.val[2]": {
        "register": "Vn+1.16B"
      },
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl3_s8",
    "arguments": [
      "int8x8x3_t a",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):a.val[2]": {
        "register": "Vn+1.16B"
      },
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl3_u8",
    "arguments": [
      "uint8x8x3_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):a.val[2]": {
        "register": "Vn+1.16B"
      },
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
      },
      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl4_p8",
    "arguments": [
      "poly8x8x4_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
      },
      "a.val[3]:a.val[2]": {
        "register": "Vn+1.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl4_s8",
    "arguments": [
      "int8x8x4_t a",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
      },
      "a.val[3]:a.val[2]": {
        "register": "Vn+1.16B"
      },
      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbl4_u8",
    "arguments": [
      "uint8x8x4_t a",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a.val[1]:a.val[0]": {
        "register": "Vn.16B"
      },
      "a.val[3]:a.val[2]": {
        "register": "Vn+1.16B"
      },
      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):b": {
        "register": "Vn.16B"
      },
      "a": {
        "register": "Vd.8B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):b": {
        "register": "Vn.16B"
      },
      "a": {
        "register": "Vd.8B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.16B"
      },
      "a": {
        "register": "Vd.8B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx2_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8x2_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
      },
      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "TBX"
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  {
    "SIMD_ISA": "Neon",
    "name": "vtbx2_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8x2_t b",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtbx2_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8x2_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBX"
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx3_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8x3_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):b.val[2]": {
        "register": "Vn+1.16B"
      },
      "a": {
        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
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      "idx": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
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    "instructions": [
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        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtbx3_s8",
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      "int8x8_t a",
      "int8x8x3_t b",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):b.val[2]": {
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      "b.val[1]:b.val[0]": {
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        "register": "Vm.8B"
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    },
    "Architectures": [
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      "A32",
      "A64"
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    "instructions": [
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        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx3_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8x3_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "Zeros(64):b.val[2]": {
        "register": "Vn+1.16B"
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        "register": "Vd.8B"
      },
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        "register": "Vm.8B"
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    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "MOVI",
        "CMHS",
        "TBL",
        "BIF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx4_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8x4_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
      },
      "b.val[3]:b.val[2]": {
        "register": "Vn+1.16B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx4_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8x4_t b",
      "int8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
      },
      "b.val[3]:b.val[2]": {
        "register": "Vn+1.16B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "TBX"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtbx4_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8x4_t b",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.8B"
      },
      "b.val[1]:b.val[0]": {
        "register": "Vn.16B"
      },
      "b.val[3]:b.val[2]": {
        "register": "Vn+1.16B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TRN1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TRN1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TRN1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_s16",
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      "int16x4_t a",
      "int16x4_t b"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "uint16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtrn1_u32",
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      "uint32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "uint8x8_t b"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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    "instructions": [
      [
        "TRN1"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t b"
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      "value": "float16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t b"
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t b"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly16x8_t b"
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      "value": "poly16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly64x2_t b"
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      "value": "poly64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      [
        "TRN1"
      ]
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    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "TRN1"
      ]
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A64"
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        "TRN1"
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      "int64x2_t b"
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      "value": "int64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN1"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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      "uint64x2_t b"
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        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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      "uint8x16_t b"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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    "instructions": [
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        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x4_t b"
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      "value": "float16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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        "TRN2"
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  {
    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "TRN2"
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  {
    "SIMD_ISA": "Neon",
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      "value": "poly16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "TRN2"
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  {
    "SIMD_ISA": "Neon",
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      "poly8x8_t b"
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      "a": {
        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "TRN2"
      ]
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    "SIMD_ISA": "Neon",
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      "int16x4_t b"
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "TRN2"
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t b"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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        "TRN2"
      ]
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    "SIMD_ISA": "Neon",
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      "uint32x2_t b"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_f16",
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      "float16x8_t b"
    ],
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      "value": "float16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "TRN2"
      ]
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    "SIMD_ISA": "Neon",
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      "float32x4_t b"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "TRN2"
      ]
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    "SIMD_ISA": "Neon",
    "name": "vtrn2q_f64",
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      "float64x2_t b"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_p16",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
    "name": "vtrn2q_p64",
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      "poly64x2_t b"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_p8",
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      "poly8x16_t b"
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      "value": "poly8x16_t"
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        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
      }
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    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "TRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN2"
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        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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        "TRN2"
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        "TRN2"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "TRN2"
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        "TRN2"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.2S"
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        "TRN2"
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        "register": "Vm.4H"
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        "TRN2"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "TRN2"
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        "TRN2"
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        "register": "Vn.2S"
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        "TRN2"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "TRN2"
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        "register": "Vn.4H"
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        "TRN2"
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        "register": "Vn.16B"
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        "register": "Dm"
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        "register": "Vn.4H"
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        "register": "Vn.2S"
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        "register": "Dn"
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        "register": "Dm"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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        "register": "Dn"
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        "register": "Dm"
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        "CMTST"
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  {
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A64"
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        "CMTST"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtstd_s64",
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      "int64_t a",
      "int64_t b"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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  {
    "SIMD_ISA": "Neon",
    "name": "vtstd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s16",
    "arguments": [
      "int16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s32",
    "arguments": [
      "int32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s64",
    "arguments": [
      "int64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s8",
    "arguments": [
      "int8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddb_s8",
    "arguments": [
      "int8_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bd"
      },
      "b": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddd_s64",
    "arguments": [
      "int64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddh_s16",
    "arguments": [
      "int16_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s16",
    "arguments": [
      "int16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s32",
    "arguments": [
      "int32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s64",
    "arguments": [
      "int64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s8",
    "arguments": [
      "int8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadds_s32",
    "arguments": [
      "int32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_laneq_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_lane_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_laneq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusmmlaq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "uint32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "UZP1"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "UZP1"
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        "register": "Vm.4S"
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        "UZP1"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "UZP1"
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        "UZP1"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "UZP1"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "UZP1"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "UZP1"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "register": "Vn.2D"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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        "register": "Vm.4H"
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        "register": "Vm.2S"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "register": "Vn.2S"
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        "register": "Vn.8B"
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    "SIMD_ISA": "Neon",
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vn.2D"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "UZP2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP2"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t b"
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "UZP2"
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    "SIMD_ISA": "Neon",
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      "uint32x4_t b"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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        "UZP2"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp2q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp2q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vxarq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int imm6"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "imm6": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__jcvt",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FJCVTZS"
      ]
    ]
  }
]
